SWIFT: A swing-reduced interconnect for a Token-based Network-On-Chip in 90nm CMOS

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2010, Pages 439-446

  Krishna, Tushar ^a   Postman, Jacob ^b   Edmonds, Christopher ^b   Peh, Li Shiuan ^a   Chiang, Patrick ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b OREGON STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; BASELINE NETWORK; CHIP MULTI-PROCESSORS; CONTROL PATH; DATA PATHS; LATENCY REDUCTION; LOW-POWER COMMUNICATION; LOW-VOLTAGE; MESH NETWORK; NETWORK ON CHIP; ON-CHIP NETWORKS; POWER SAVINGS;

COMPUTER GRAPHICS; DESIGN; MESH NETWORKING; SERVERS; VLSI CIRCUITS;

ROUTERS;

EID: 78650730068     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2010.5647666     Document Type: Conference Paper

References (14)

1. J. A. Kahle et al., "Introduction to the Cell multiprocessor, " IBM Journal of Research and Development, vol. 49, no. 4/5, 2005.
2. M. B. Taylor et al., "The raw microprocessor: A computational fabric for software circuits and general-purpose programs, " IEEE Micro, vol. 22, no. 2, pp. 25-35, 2002.
3. P. Gratz et al., "On-chip interconnection networks of the TRIPS chip, " IEEE Micro, vol. 27, no. 5, pp. 41-50, Sept. 2007.
4. Y. Hoskote et al., "A 5-GHz mesh interconect for a teraflops processor, " IEEE Micro, vol. 27, no. 5, pp. 51-61, Sept. 2007.
5. A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha, "Express virtual channels: Towards the ideal interconnection fabric, " in Proc. Int. Symp. Computer Architecture, June 2007.
6. A. Kumar, L.-S. Peh, and N. K. Jha, "Token flow control, " in Proc. 41st International Symposium on Microarchitecture, November 2008.
7. J. Bae, J.-Y. Kim, and H.-J. Yoo, "A 0.6pj/b 3gb/s/ch transceiver in 0.18 um cmos for 10mm on-chip interconnects, " in IEEE International Symposium on Circuits and Systems, May 2008, pp. 2861-2864.
8. B. Kim and V. Stojanovic, "A 4gb/s/ch 356fj/b 10mm equalized onchip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm cmos, " IEEE International Solid- State Circuits Conference,, pp. 66-68, Feb. 2009.
9. K. Lee, S.-J. Lee, and H.-J. Yoo, "Low-power network-on-chip for high-performance soc design, " IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, pp. 148-160, 2006.
10. H.-S. Wang, L.-S. Peh, and S. Malik, "Power-driven design of router microarchitectures in on-chip networks, " in Proc. Int. Symp. Microarchitecture, Nov. 2003, pp. 105-116.
11. W. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Pub., 2003.
12. W. J. Dally, "Virtual-channel flow control, " in Proc. Int. Symp. Computer Architecture, May 1990, pp. 60-68.
13. A. Kumar et al., "A 4.6Tbits/s 3.6GHz single-cycle noc router with a novel switch allocator in 65nm CMOS, " in Proc. Int. Conf. Computer Design, Oct. 2007.
14. M. Galles, "Scalable pipelined interconnect for distributed endpoint routing: The SGI SPIDER chip." in Proc. Hot Interconnects 4, Aug. 1996.