Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 71-82

  Krishna, Tushar ^a   Peh, Li Shiuan ^a   Beckmann, Bradford M ^b   Reinhardt, Steven K ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b AMD Research   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE COHERENCE; DATA COHERENCE; FAN-OUT; FLOW AGGREGATION; FULL-SYSTEM SIMULATION; IDEAL NETWORK; MULTICAST PACKET; MULTICORE ARCHITECTURES; ON CHIPS; ON-CHIP NETWORKS; PACKET DELAY; POWER PENALTY; RUNTIMES; SINGLE CYCLE; WIRE DELAYS;

COMMUNICATION; EMBEDDED SYSTEMS; SOFTWARE ARCHITECTURE;

ROUTERS;

EID: 84858790896     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155630     Document Type: Conference Paper

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