메뉴 건너뛰기




Volumn , Issue , 1991, Pages 51-61

Two-level adaptive training branch prediction

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; PIPELINES; PROGRAM PROCESSORS;

EID: 85034094146     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/123465.123475     Document Type: Conference Paper
Times cited : (331)

References (18)
  • 4
    • 85054818422 scopus 로고
    • Motorola Inc Phoenix, Arizona, March 13
    • Motorola Inc., "M88100 User's Manual", Phoenix, Arizona, (March 13, 1989).
    • (1989) M88100 User's Manual
  • 7
    • 0024035849 scopus 로고
    • Reducing the branch penalty in pipelined processors
    • July
    • D. J. Lilja, "Reducing the Branch Penalty in Pipelined Processors ", IEEE Computer, (July 1988), pp.47-55.
    • (1988) IEEE Computer , pp. 47-55
    • Lilja, D.J.1
  • 8
    • 0023587656 scopus 로고
    • Checkpoint repair for out-of-order execution machines
    • December
    • W.W. Hwu and Y.N. Patt, ", Checkpoint Repair for Out-of-order Execution Machines", IEEE Transactions on Computers, (December 1987), pp. 1496-1514.
    • (1987) IEEE Transactions on Computers , pp. 1496-1514
    • Hwu, W.W.1    Patt, Y.N.2
  • 9
    • 0023386285 scopus 로고
    • Characterization of branch and data dependencies in programs for evaluating pipeline performance
    • July
    • P. G. Emma and E. S. Davidson, ", Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance", IEEE Transactions on Computers, (July 1987), pp.859-876.
    • (1987) IEEE Transactions on Computers , pp. 859-876
    • Emma, P.G.1    Davidson, E.S.2
  • 13
    • 0021204160 scopus 로고
    • Branch prediction strategies and branch target buffer design
    • January
    • J. Lee and A. J. Smith, ", Branch Prediction Strategies and Branch Target Buffer Design", IEEE Computer, (January 1984), pp.6-22.
    • (1984) IEEE Computer , pp. 6-22
    • Lee, J.1    Smith, A.J.2
  • 17
    • 84937647458 scopus 로고
    • A multiminipro-cessor system implemented through pipelining
    • Feb
    • L.E. Shar and E.S. Davidson, ", A Multiminipro-cessor System Implemented Through Pipelining.", IEEE Computer, (Feb. 1974), pp.42-51.
    • (1974) IEEE Computer , pp. 42-51
    • Shar, L.E.1    Davidson, E.S.2
  • 18
    • 0014995747 scopus 로고
    • Parallelism, pipelining and computer efficiency
    • Jan
    • T. C. Chen, "Parallelism, Pipelining and Computer Efficiency", Computer Design, Vol. 10, No. 1, (Jan. 1971), pp.69-74
    • (1971) Computer Design , vol.10 , Issue.1 , pp. 69-74
    • Chen, T.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.