A monolithically-integrated optical receiver in standard 45-nm SOI

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 7, 2012, Pages 1693-1702

  Georgas, Michael ^a   Orcutt, Jason ^a   Ram, Rajeev J ^a   Stojanovic, Vladimir ^a  

^a Department of Electrical Engineering and Computer Science   (United States)

Author keywords

chip to chip links; high speed I O; integrating receivers; interconnect; many core; monolithic integration; multi core; Photonics; sense amplifiers; SOI; transimpedance amplifiers

Indexed keywords

CHIP-TO-CHIP LINKS; HIGH SPEED I/O; INTERCONNECT; MANY-CORE; MONOLITHIC INTEGRATION; MULTI CORE; SENSE AMPLIFIER; SOI; TRANSIMPEDANCE AMPLIFIERS;

CAPACITANCE; DIFFERENTIAL AMPLIFIERS; PHOTODIODES; PHOTONICS;

MONOLITHIC INTEGRATED CIRCUITS;

EID: 84862999102     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2191684     Document Type: Article

References (22)

1. C. Batten, A. Joshi, J. Orcutt, C. Holzwarth, M. Popovic, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, "Building manycore processor-to-DRAM networks with monolithic CMOS silicon photonics," IEEE Micro, vol. 29, no. 4, pp. 8-21, Jul.-Aug. 2009.
2. C. Kromer, G. Sialm, T. Morf, M. Schmatz, F. Ellinger, D. Erni, and H. Jackel, "A low-power 20-GHz 52-dB-Ohm transimpedance amplifier in 80-nm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 885-894, Jun. 2004.
3. A. Emami-Neyestanak, D. Liu, G. Keeler, N. Helman, and M. Horowitz, "A 1.6 Gb/s, 3 mW CMOS receiver for optical communication," in Symp. VLSI Circuits Dig. Tech. Papers, 2002, pp. 84-87.
4. I. Young, E. Mohammed, J. Liao, A. Kern, S. Palermo, B. Block, M. Reshotko, and P. Chang, "Optical I/O technology for tera-scale computing," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 235-248, Jan. 2010.
5. A. Rylyakov, C. Schow, B. Lee, W. Green, J. Van Campenhout, M. Yang, F. Doany, S. Assefa, C. Jahnes, J. Kash, and Y. Vlasov, "A 3.9 ns 8.9 mw 4 4 silicon photonic switch hybrid integrated with CMOS driver," in IEEE ISSCC Dig., 2011, pp. 222-224.
6. G. Li et al., "Ultralow-power silicon photonic interconnect for high-performance computing systems," in Proc. SPIE Optoelectronic Interconnects and Component Integration IX, 2010, vol. 7607, pp. 703-760.
7. F. Liu, D. Patil, J. Lexau, P. Amberg, M. Dayringer, J. Gainsley, H. Moghadam, X. Zheng, J. Cunningham, A. Krishnamoorthy, E. Alon, and R. Ho, "10 Gbps, 530 fJ/b optical transceiver circuits in 40 nm CMOS," in Symp. VLSI Circuits Dig., 2011, pp. 290-291.
8. K. Fukuda, H. Yamashita, G. Ono, R. Nemoto, E. Suzuki, N. Masuda, T. Takemoto, F. Yuki, and T. Saito, "A 12.3-mW 12.5-Gb/s complete transceiver in 65-nm CMOS process," IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2838-2849, Dec. 2010.
9. M. Georgas, J. Leu, B. Moss, C. Sun, and V. Stojanovic, "Addressing link-level design tradeoffs for integrated photonic interconnects," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2011, pp. 1-8.
10. J. S. Yun,M. Seo, B. Choi, J. Han, Y. Eo, and S. M. Park, "A 4 Gb/s current-mode optical transceiver in 0.18 m CMOS," in IEEE ISSCC Dig., 2009, pp. 102-103.
11. A.Narasimha, B.Analui, Y. Liang, T. Sleboda, and C. Gunn, "A fully integrated 4 10 Gb/sDWDMoptoelectronic transceiver in a standard 0.13 m CMOS SOI," in IEEE ISSCC Dig., 2007, pp. 42-586.
12. K.-L.Wong and C.-K.Yang, "Offset compensation in comparators with minimum input-referred supply noise," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 837-840, May 2004.
13. S.-H. Woo, H. Kang, K. Park, and S.-O. Jung, "Offset voltage estimation model for latch-type sense amplifiers," IET Circuits, Devices Syst., vol. 4, no. 6, pp. 503-513, 2010.
14. E. Alon, V. Stojanovic, and M. Horowitz, "Circuits and techniques for high-resolution measurement of on-chip power supply noise," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 820-828, Apr. 2005.
15. S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, and M. Horowitz, "The implementation of a 2-core, multithreaded Itanium family processor," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 197-209, Jan. 2006. (Pubitemid 43145977)
16. S. Palermo, A. Emami-Neyestanak, and M. Horowitz, "A 90 nm CMOS 16 Gb/s transceiver for optical interconnects," IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1235-1246, May 2008. (Pubitemid 351596354)
17. S. Assefa, F. Xia, W. Green, C. Schow, A. Rylyakov, and Y. Vlasov, "CMOS-integrated optical receivers for on-chip interconnects," IEEE J. Sel. Topics Quantum Electron., vol. 16, no. 5, pp. 1376-1385, Sep. -Oct. 2010.
18. J. Polleux and C. Rumelhard, "Optical absorption coeficient determination and physical modelling of strained SiGe/Si photodetectors," in 8th IEEE Int. Symp. High Performance Electron Devices for Microwave and Optoelectronic Applications, 2000, pp. 167-172. (Pubitemid 32451439)
19. S. Mukhopadhyay, R. Joshi, K. Kim, and C.-T. Chuang, "Variability analysis for sub-100 nm PD/SOI sense-amplifier," in Proc. ISQED, 2008, pp. 488-491.
20. J.-S.Kim, C. S. Oh,H. Lee,D. Lee,H.-R. Hwang, S. Hwang, B. Na, J. Moon, J.-G. Kim, H. Park, J.-W. Ryu, K. Park, S.-K. Kang, S.-Y. Kim, H. Kim, J.-M. Bang, H. Cho, M. Jang, C. Han, J.-B. Lee, K. Kyung, J.-S. Choi, and Y.-H. Jun, "A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4 128 I/Os using TSV-based stacking," in IEEE ISSCC Dig., 2011, pp. 496-498.
21. M. Jeeradit, J. Kim, B. Leibowitz, P. Nikaeen, V. Wang, B. Garlepp, and C.Werner, "Characterizing sampling aperture of clocked comparators," in Symp. VLSI Circuits Dig., 2008, pp. 68-69.
22. S. Goswami, J. Silver, T. Copani, W. Chen, H. Barnaby, B. Vermeire, and S. Kiaei, "A 14 mW 5 Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects," in IEEE ISSCC Dig., 2009, pp. 100-101, 101a.