A 12.3-mW 12.5-Gb/s complete transceiver in 65-nm CMOS process

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 12, 2010, Pages 2838-2849

  Fukuda, Koji ^a   Yamashita, Hiroki ^a   Ono, Goichi ^a   Nemoto, Ryo ^a   Suzuki, Eiichi ^a   Masuda, Noboru ^a   Takemoto, Takashi ^a   Yuki, Fumio ^a   Saito, Tatsuya ^a  

^a HITACHI LTD   (Japan)

Author keywords

Low power; serial link; transceiver

Indexed keywords

CLOCK DISTRIBUTION; CMOS PROCESSS; CONSUMING POWER; DIGITAL CMOS; GLOBAL CLOCKS; LOW POWER; LOW SWING; MULTIPLEXER/DEMULTIPLEXER (MUX/DEMUX); ONCHIP INDUCTORS; PHASE DETECTORS; POWER CONSUMPTION; PULSE CURRENTS; SENSE AMPLIFIER; SERIAL LINK; VARIABLE DELAYS;

ANTENNA PHASED ARRAYS; BIT ERROR RATE; CLOCKS; CMOS INTEGRATED CIRCUITS; DISTRIBUTED PARAMETER NETWORKS; ELECTRIC INDUCTORS; PHASE LOCKED LOOPS;

TRANSCEIVERS;

EID: 78650037410     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2075410     Document Type: Conference Paper

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