A 4Gb/s current-mode optical transceiver in 0.18μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 102-103

  Yun, Ji Sook ^a   Seo, Mikyung ^a   Choi, Booyoung ^a   Han, Jungwon ^a   Eo, Yunsung ^b   Park, Sung Min ^a  

^a Ewha Womans University   (South Korea)

^b Kwangwoon University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349292815     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977328     Document Type: Conference Paper

References (5)

1. J. Han, B. Choi, K. Park, et al., "A 2.5Gb/2 ESD-Protected Dual-Channel Optical Transceiver Array, " IEEE ASSCC, pp. 156-159, Jul., 2007.
2. K. Yoo, D. Lee, G. Han, et al., "A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation, " ISSCC Dig. Tech. Papers, pp. 56-57, Feb., 2007.
3. S. Rabii, N. Acharya, P. Chau, et al., "An Integrated VCSEL Driver for 10Gb Ethernet in 0.13μm CMOS, " ISSCC Dig. Tech. Papers, pp. 930-939, Feb., 2006.
4. W.-Z. Chen, Y.-L Cheng, and D.-S. Lin, "A 1.8-V 10-Gb/s Fully Integrated CMOS Optical Receiver Analog Front-End, " IEEE J. Solid-State Circuits, vol.40, no.6, pp. 1388- 1396, Jun., 2005.
5. C.-M. Tsai and W.-T. Chen, "A 40mW 3.5kΩ 3Gb/s CMOS Differential Transimpedance Amplifier Using Negative-Impedance Compensation, " ISSCC Dig. Tech. Papers, pp. 52- 53, Feb., 2007.