A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages

  Goswami, Sushmit ^a   Silver, Jason ^a   Copani, Tino ^a   Chen, Wenjian ^a   Barnaby, Hugh J ^a   Vermeire, Bert ^a   Kiaei, Sayfe ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349291223     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977327     Document Type: Conference Paper

References (2)

1. C. Kromer, G. Sialm, C. Berger, et al., "A 100mW 4×10Gb/s Transceiver in 80nm CMOS for High-Density Optical Interconnects, " ISSCC Dig. Tech. Papers, pp. 334-602, Feb., 2005.
2. S.M. Park and H.-J. Yoo, "1.25-Gb/s Regulated Cascode CMOS Trans-Impedance Amplifier for Gigabit Ethernet Applications, " IEEE J. Solid-State Circuits, vol.39, no.1, pp. 112-121, Jan., 2004.