A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 7, 2012, Pages 1784-1796

  Rooseleer, Bram ^a   Cosemans, Stefan ^b   Dehaene, Wim ^a,b  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b IMEC   (Belgium)

Author keywords

Configurable timing; dynamic decoder; dynamic stability; local bit lines; local sense amplifiers; local word lines; low leakage cell; low power circuit design; low swing signalling; SRAM; variability aware design

Indexed keywords

BIT LINES; CONFIGURABLE TIMING; LOCAL SENSE AMPLIFIERS; LOCAL WORD LINES; LOW LEAKAGE; LOW SWING; LOW-POWER CIRCUIT DESIGN; VARIABILITY-AWARE DESIGN;

CELLS; CYTOLOGY; DESIGN; ENERGY UTILIZATION; LOW POWER ELECTRONICS; STABILITY;

STATIC RANDOM ACCESS STORAGE;

EID: 84862987071     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2191316     Document Type: Article

References (27)

1. W. Dehaene, G. Gielen, M. Steyaert, H. Danneels, V. Desmedt, C. De Roover, Z. Li, M. Verhelst, N. Van Helleputte, S. Radiom, C. Walravens, and L. Pleysier, "RFID, where are they?," in Proc. ESSCIRC, 2009, pp. 36-43.
2. K. Masselos, F. Catthoor, C. Goutis, and H. Deman, "A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 4, pp. 515-518, Aug. 2002.
3. M. De Nil, L. Yseboodt, F. Bouwens, J. Hulzink, M. Berekovic, J. Huisken, and J. van Meerbergen, "Ultra low power ASIP design for wireless sensor nodes," in Proc. 14th IEEE Int. Conf. Electronics, Circuits and Systems, ICECS 2007, 2007, pp. 1352-1355.
4. B. Rooseleer, S. Cosemans, andW. Dehaene, "A 65 nm, 850MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link," in Proc. ESSCIRC, 2011, pp. 519-522.
5. M. Yoshimoto, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano, and T. Nakano, "A divided word-line structure in the static RAM and its application to a 64 k full CMOS RAM," IEEE J. Solid-State Circuits, vol. SC-18, no. 5, pp. 479-485, Oct. 1983. (Pubitemid 14506592)
6. T. Hirose, H. Kuriyama, S.Murakami, K. Yuzuriha, T.Mukai, K. Tsutsumi, Y. Nishimura, Y. Kohno, and K. Anami, "A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture," IEEE J. Solid-State Circuits, vol. 25, no. 5, pp. 1068-1074, Oct. 1990.
7. A. Karandikar and K. Parhi, "Low power SRAM design using hierarchical divided bit-line approach," in Proc. Int. Conf. Computer Design: VLSI in Computers and Processors, ICCD'98, Oct. 1998, pp. 82-88.
8. B.-D. Yang and L.-S. Kim, "A low-power SRAM using hierarchical bit line and local sense amplifiers," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1366-1376, Jun. 2005. (Pubitemid 40819379)
9. S. Ishikura, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi,K.Nii,M.Yabuuchi,Y. Tsukamoto, S.Ohbayashi, T. Oashi, H. Makino, H. Shinohara, and H. Akamatsu, "A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 938-945, Apr. 2008.
10. S. Cosemans, "Variability-aware design of low power SRAM memories," Ph.D. dissertation, KU Leuven, Leuven, Belgium, 2009.
11. T. Sakurai, "High-speed circuit design with scaled-down MOSFETs and low supply voltage," in Proc. IEEE Int. Symp. Circuits and Systems, ISCAS'93, May 1993, vol. 3, pp. 1487-1490. (Pubitemid 23699097)
12. E. Seevinck, F. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. 22, no. 5, pp. 748-754, Oct. 1987. (Pubitemid 18521731)
13. H. Zhu and V. Kursun, "Application-specific selection of 6T SRAM cells offering superior performance and quality with a triple- thresholdvoltageCMOStechnology," in Proc. 3rd Asia Symp.Quality Electronic Design (ASQED), Jul. 2011, pp. 68-73.
14. S. Cosemans, W. Dehaene, and F. Catthoor, "A low power embedded SRAM for wireless applications," in Proc. 32nd ESSCIRC, 2006, pp. 291-294.
15. S. Cosemans, W. Dehaene, and F. Catthoor, "A low-power embedded SRAM for wireless applications," IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1607-1617, Jul. 2007. (Pubitemid 47000225)
16. S. Cosemans,W. Dehaene, and F. Catthoor, "A 3.6 pJ/access 480MHz, 128 kb on-chip SRAMwith 850 MHz boostmode in 90 nmCMOSwith tunable sense amplifiers," IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2065-2077, Jul. 2009.
17. V. Sharma, S. Cosemans, M. Ashouei, J. Huisken, F. Catthoor, and W. Dehaene, "A 4.4 pJ/access 80 MHz, 2 K word 64 b memory with write masking feature and variability resilient multi-sized sense amplifier redundancy for wireless sensor nodes applications," in Proc. ESSCIRC, 2010, pp. 358-361.
18. N. Verma and A. Chandrakasan, "A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141-149, Jan. 2008.
19. M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
20. H. Nambu, K. Kanetani, K. Yamasaki, K. Higeta, M. Usami, T. Kusunoki, K. Yamaguchi, and N. Homma, "A 1.8 ns access, 550 MHz 4.5Mb CMOS SRAM," in IEEE ISSCC Dig., 1998, pp. 360-361, 464.
21. T. Suzuki, S. Nakahara, S. Iwahashi, K. Higeta, K. Kanetani, H. Nambu, M. Yoshida, and K. Yamaguchi, "Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core," in Symp. VLSI Circuits Dig. Tech. Papers, 2002, pp. 44-45.
22. Y. Wang, H. J. Ahn, U. Bhattacharya, Z. Chen, T. Coan, F. Hamzaoglu, W. Hafez, C.-H. Jan, P. Kolar, S. Kulkarni, J.-F. Lin, Y.-G. Ng, I. Post, L. Wei, Y. Zhang, K. Zhang, and M. Bohr, "A 1.1 GHz 12 A Mb-leakage SRAM design in 65 nm ultra-low-power CMOS technology with integrated leakage reduction for mobile applications," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 172-179, Jan. 2008.
23. K. Kushida, A. Suzuki, G. Fukano, A. Kawasumi, O. Hirabayashi, Y. Takeyama, T. Sasaki, A. Katayama, Y. Fujimura, and T. Yabe, "A 0.7 V single-supply SRAM with 0.495 m cell in 65 nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1192-1198, 2009.
24. M. Sinangil, N. Verma, and A. Chandrakasan, "A reconfigurable 65 nm SRAM achieving voltage scalability from 0.25-1.2 V and performance scalability from 20 kHz-200MHz," in Proc. 34th ESSCIRC, 2008, pp. 282-285.
25. M.-H. Chang, Y.-T. Chiu, S.-L. Lai, and W. Hwang, "A 1 kb 9T subthreshold SRAM with bit-interleaving scheme in 65 nm CMOS," in Proc. Int. Symp. Low Power Electronics and Design (ISLPED), 2011, pp. 291-296.
26. S. Wu, X. Zheng, Z. Gao, and X. He, "A 65 nm embedded low power SRAM compiler," in Proc. 13th IEEE Int. Symp. Design and Diagnostics of Electronic Circuits and Systems (DDECS), Apr. 2010, pp. 123-124.
27. G. Fukano, K. Kushida, A. Tohata, Y. Takeyama, K. Imai, A. Suzuki, T. Yabe, and N. Otsuka, "A 65 nm 1 Mb SRAM macro with dynamic voltage scaling in dual power supply scheme for low power SoCs," in Joint Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design, NVSMW/ICMTD , May 2008, pp. 97-98.