A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link

European Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 519-522

  Rooseleer, Bram ^a   Cosemans, Stefan ^a,b   Dehaene, Wim ^a,b  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE ENERGY; BITLINES; CELL STABILITY; CMOS PROCESSS; DATA LINK; HIGH-THRESHOLD VOLTAGES; LEAKAGE POWER; LOW LEAKAGE POWER; LOW POWER; NOVEL TECHNIQUES; SENSE AMPLIFIER; SRAM MEMORIES; WORD LENGTH;

CELLS; CMOS INTEGRATED CIRCUITS; DECODING; ENERGY UTILIZATION;

STATIC RANDOM ACCESS STORAGE;

EID: 82955241418     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2011.6044936     Document Type: Conference Paper

References (9)

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