Low-resistance Cu-Sn electroplated-evaporated microbumps for 3D chip stacking

Journal of Electronic Materials

Volumn 41, Issue 4, 2012, Pages 720-729

  Murugesan, M ^a   Ohara, Y ^a   Fukushima, T ^a   Tanaka, T ^a   Koyanagi, M ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Cu Sn; microbump; microstructure; resistivity

Indexed keywords

BONDING TEMPERATURES; CHIP STACKING; CRYSTAL GRAIN ORIENTATION; CU-SN; ELECTRICAL RESISTANCES; ELECTRON BACKSCATTER DIFFRACTION ANALYSIS; GRAIN SIZE; IMPURITY SEGREGATION; LAYER-BY-LAYER GROWTH; LOW RESISTANCE; MICRO-BUMPS; PHYSICAL VAPOR DEPOSITED; RESISTANCE VALUES; SN GRAINS; THREE DIMENSIONAL INTEGRATION; X-RAY DIFFRACTION DATA;

CRYSTAL IMPURITIES; CRYSTAL ORIENTATION; ELECTRIC CONDUCTIVITY; ELECTRON PROBE MICROANALYSIS; ELECTROPLATING; GRAIN BOUNDARIES; MICROSTRUCTURE; SURFACE ROUGHNESS; X RAY DIFFRACTION;

TIN;

EID: 84862780126     PISSN: 03615235     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11664-012-1949-1     Document Type: Article

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