Micro Cu bump Interconnection on 3D chip stacking technology

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 43, Issue 4 B, 2004, Pages 2264-2270

  Tanida, Kazumasa ^a   Umemoto, Mitsuo ^a   Tanaka, Naotaka ^a   Tomita, Yoshihiro ^a   Takahashi, Kenji ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

Chip on chip (COC); Cu bump bonding (CBB); Cu through via (TV); Cu sn; Interconnection; Intermetallic compound (IMC); Nano indentation; System in package (SIP); Three dimensional (3D) chip stacking LSI

Indexed keywords

ELASTIC MODULI; ELECTRIC RESISTANCE; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; INTERMETALLICS; MICROPROCESSOR CHIPS; SCANNING ELECTRON MICROSCOPY; STACKING FAULTS; ULSI CIRCUITS;

CHIP-ON-CHIP (COC); CU BUMP BONDING (CBB); CU THROUGH-VIA (TV); INTERCONNECTIONS; NANO-INDENTATION; SYSTEM IN PACKAGE (SIP); THREE DIMENSIONAL CHIP STACKING LSI;

LSI CIRCUITS;

EID: 3142539017     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.43.2264     Document Type: Conference Paper

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