Buried silicon-germanium pMOSFETs: Eanalysis in VLSI logic circuits under aggressive voltage scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 8, 2012, Pages 1487-1495

  Crupi, Felice ^a   Alioto, Massimo ^b,c   Franco, Jacopo ^d,e   Magnone, Paolo ^f   Kaczer, Ben ^d   Groeseneken, Guido ^d,e   Mitard, Jéröme ^f   Witters, Liesbeth ^d   Hoffmann, Thomas Y ^d  

^a UNIVERSITY OF CALABRIA   (Italy)

^b UNIVERSITY OF SIENA   (Italy)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d IMEC   (Belgium)

^e UNIVERSITY OF LEUVEN   (Belgium)

^f UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Aggressive voltage scaling; digital circuits; emerging technologies; energy efficiency; power delay trade off; Silicon Germanium; VLSI

Indexed keywords

EMERGING TECHNOLOGIES; POWER-DELAY TRADEOFF; SILICON GERMANIUM; VLSI; VOLTAGE-SCALING;

DIGITAL CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; ENERGY EFFICIENCY; GERMANIUM; HETEROJUNCTION BIPOLAR TRANSISTORS; INNOVATION; LOGIC CIRCUITS; LOGIC GATES; MOSFET DEVICES; SILICON; SILICON ALLOYS; TECHNOLOGY;

VLSI CIRCUITS;

EID: 84862684939     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2159870     Document Type: Article

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