Demonstration of high-performance PMOSFETs Using Si-Six Ge1-x-Si quantum wells with high-κ metal-gate stacks

IEEE Electron Device Letters

Volumn 29, Issue 1, 2008, Pages 99-101

  Majhi, Prashant ^a   Kalra, P ^a   Harris, R ^a   Choi, K J ^b,c   Heh, D ^a   Oh, J ^a   Kelly, D ^d   Choi, R ^a   Cho, B J ^b   Banerjee, S ^d   Tsai, W ^e   Tseng, H ^a   Jammy, R ^a  

^a SEMATECH   (United States)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c Jusung Engineering Company Limited   (South Korea)

^d UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^e INTEL CORPORATION   (United States)

Author keywords

High obility; High gate dielectric; PMOSFETs; Quantum wells (QWs); Silicon germanium (SiGe)

Indexed keywords

GATE DIELECTRICS; HETEROJUNCTIONS; LATTICE CONSTANTS; LEAKAGE CURRENTS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR QUANTUM WELLS;

LATTICE CONSTANT MISMATCH; METAL-GATE STACKS; STRAINED QUANTUM WELLS;

MOSFET DEVICES;

EID: 37549024971     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.911987     Document Type: Article

References (11)

1. R. Chau, "Benchmarking nanotechnology for high performance and low-power logic transistor applications," in Proc. IEEE Conf. Nanotechnology, 2004, pp. 3-6.
2. M.-L. Lee, E. A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochtefeld, "Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors," J. Appl. Phys. vol. 97, no. 1, pp. 011 101(1)-011 101(27), Jan. 2005. and references therein.
3. T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, and K. C. Saraswat, "High-mobility low hand-to-hand tunneling strained-Germanium double-gate heterostructure FETs: Simulations," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1000-1009, May 2006.
4. D. J. Eaglesham and M. Cerullo, "Dislocation-free Stranski-Krastanow growth of Ge on Si(100)," Phys. Rev. Lett., vol. 64, no. 16, pp. 1943-1946, Apr. 1990.
5. 2 nanotemplate using solid source molecular beam epitaxy," Appl. Phys. Lett., vol. 83, no. 24, pp. 5032-5034, Dec. 2003.
6. J.-S. Park, J. Bai, M. Curtin, B. Adekore, M. Carroll, and A. Lochtefeld, "Defect reduction of selective Ge epitaxy in trenches on Si (001) substrates using aspect ratio trapping," Appl. Phys. Lett., vol. 90, no. 5, pp. 052 113-052 116, Jan. 2007.
7. 1-x/Si strained-layer heterostructures," Appl. Phys. Lett., vol. 47, no. 3, pp. 322-324, Aug. 1985.
8. R. Loo, M. Caymax, P. Meunier-Beillard, I. Peytiera, F. Holsteyns, S. Kubicek, P. Verheyen, R. Lindsay, and O. Richard, "A new technique to fabricate ultra-shallow-junctions, combining in situ vapour HCl etching and in situ doped epitaxial SiGe re-growth," Appl. Surf. Sci., vol. 224, no. 1-4, pp. 63-67, Mar. 2004.
9. H. R. Harris, P. Kalra, P. Majhi, M. Hussain, D. Kelly, J. Oh, D. He, C. Smith, J. Barnett, P. D. Kirsch, G. Gebara, J. Jur, D. Lichtenwalner, A. Lubow, T. P. Ma, G. Sung, S. Thompson, B. H. Lee, H.-H. Tseng, and R. Jammy, "Band-engineered low PMOS VT with high-k/metal gates featured in a dual channel CMOS integration scheme," in VLSI Symp. Tech. Dig., 2007, pp. 154-155.
10. P. Zimmerman, G. Nicholas, B. Jauger, B. Kaczer, A. Stesmans, L. Rahnarsson, D. Brunco, F. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. Heyns, "High performance Ge pMOS devices using a Si-compatible process flow," in IEDM Tech. Dig., 2006, pp. 655-658.
11. S. C. Song, Z. B. Zhang, M. M. Hussain, C. Huffman, J. Barnett, S. H. Bae, H. J. Li, P. Majhi, C. S. Park, B. S. Ju, H. K. Park, C. Y. Kang, R. Choi, P. Zeitzoff, H. H. Tseng, B. H. Lee, and R. Jammy, "Highly manufacturable 45 nm LSTP CMOSFETs using novel dual high-k and dual metal gate CMOS integration," in VLSI Symp. Tech. Dig., 2006, pp. 13-14.