Influence of the Ge-concentration and RTA on the device performance of strained Si/SiGe pMOS devices

European Solid-State Device Research Conference

Volumn , Issue , 2002, Pages 263-266

  Collaert, N ^a   Verheyen, P ^a,b   De Meyer, K ^a,b   Loo, R ^a   Caymax, M ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

DEEP SUB-MICRON; DEVICE PERFORMANCE; PMOS DEVICES; SHORT-CHANNEL EFFECT; SI/SIGE; STANDARD CMOS TECHNOLOGY; STRAINED-SI/SIGE;

GERMANIUM;

EID: 84907681316     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2002.194920     Document Type: Conference Paper

References (5)

1. Y.-C. Yeo, Q. Lu, T.-J. King, C. Hu, T. Kawashima, M. Oishi, S. Mashiro and J. Sakai, "Enhanced Performance in Sub-100 nm CMOSFETs using Strained Epitaxial Silicon-Germanium", Proc. IEDM, 2000, pp. 753-756.
2. T.E. Whall and E.H.C. Parker, "SiGe heterostructures for FET applications", J. Phys. D., vol. 31, no. 12, 1998, pp. 1397-1416
3. R.J.P. Lander, Y.V. Ponomarev, J.G.M. van Berkum, W.B. de Boer, R. Loo, and M. Caymax, "Drift mobilities and Hall scattering factors of holes in ultrathin Si1-xGex layers (0.3 < x < 0.4) grown on Si", Journal of Applied Physics, vol. 88, August 2000, pp. 2016-2023
4. N. Collaert, P. Verheyen, K. De Meyer, R. Loo and M. Caymax, "High performance Si/SiGe pMOSFETs fabricated in a standard CMOS process technology", Proc. ULIS workshop 2002, Munich, p. 77- 80
5. John R. Hauser, IEEE Trans. Electron Dev., vol. 43, no. 11, November 1996, pp. 1981-1988