Enhancing effective throughput for transmission line-based bus

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 165-176

  Carpenter, Aaron ^b   Hu, Jianyun ^a   Kocabas, Ovunc ^a   Huang, Michael ^a   Wu, Hui ^a  

^a University of Rochester   (United States)

^b BINGHAMTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUS ARCHITECTURE; CHIP MULTIPROCESSOR; DATA MOVEMENTS; EFFECTIVE THROUGHPUT; GENERAL-PURPOSE MICROPROCESSORS; LOWER ENERGIES; NETWORK-ON-CHIP ARCHITECTURES; ON CHIP INTERCONNECT; SCALABLE SOLUTION;

COMPUTER ARCHITECTURE; ELECTRIC LINES; MICROPROCESSOR CHIPS; TRANSMISSION LINE THEORY; VLSI CIRCUITS;

BUSES;

EID: 84862328694     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237015     Document Type: Conference Paper

References (45)

1. http://www.sonnetsoftware.com/.
2. PoPNet. http://www.princeton.edu/~peh/orion.html.
3. Predictive Technology Modeling. http://ptm.asu.edu/.
4. T. Ainsworth and T. Pinkston. Characterizing the Cell EIB On-Chip Network. IEEE Micro, 27(5):6-14, 2007.
5. J. Balfour and W. J. Dally. Design Tradeoffs for Tiled CMP On-Chip Networks. In Proc. Int'l Conf. on Supercomputing, pages 187-198, June 2006.
6. B. Beckmann and D. Wood. TLC: Transmission Line Caches. In Proc. Int'l Symp. on Microarch., pages 43-54, December 2003.
7. B. Beckmann and D. Wood. Managing Wire Delay in Large Chip-Multiprocessor Caches. In Proc. Int'l Symp. on Microarch., pages 319-330, November 2004.
8. C. Bienia, S. Kumar, J. Singh, and K. Li. The PAR SEC Benchmark Suite: Characterization and Architectural Implications. In Proc. Int'l Conf. on Parallel Arch. and Compilation Techniques, September 2008.
9. D. Burger and T. Austin. The SimpleScalar Tool Set, Version 2.0. Technical report 1342, Computer Sciences Department, University of Wisconsin-Madison, June 1997.
10. A. Carpenter, J. Hu, M. Huang, H. Wu, and P. Liu. A Design Space Exploration for of Transmission-Line Links for On-Chip Interconnect. In Proc. Int'l Symp. on Low-Power Electronics and Design, pages 265-270, August 2011.
11. A. Carpenter, J. Hu, J. Xu, M. Huang, and H.Wu. A Case for Globally Shared-Medium On-Chip Interconnect. In Proc. Int'l Symp. on Comp Arch., June 2011.
12. M. Chang, J. Cong, A. Kaplan, C. Liu, M. Naik, J. Premkumar, G. Reinman, E. Socher, and S. Tam. Power Reduction of CMP Communication Networks via RF-Interconnects. In Proc. Int'l Symp. on Microarch., pages 376-387, November 2008.
13. M. Chang, J. Cong, A. Kaplan, M. Naik, G. Reinman, E. Socher, and R. Tam. CMP Network-on-Chip Overlaid With Multi-Band RFInterconnect. In Proc. Int'l Symp. on High-Perf. Comp. Arch., pages 191-202, February 2008.
14. M. Chang, E. Socher, S. Tam, J. Cong, and G. Reinman. RF Interconnects for Communications On-chip. In Proc. Int'l Symp. on Physical Design, pages 78-83, April 2008.
15. R. Chang, N. Talwalkar, C. Yue, and S. Wong. Near Speed-of-Light Signaling Over On-Chip Electrical Interconnects. IEEE Journal of Solid-State Circuits, 38(5):834-838, May 2003.
16. M. Cianchetti, J. Kerekes, and D. Albonesi. Phastlane: A rapid transit optical routing network. In Proc. Int'l Symp. on Comp. Arch., pages 441-450, June 2009.
17. D. Culler, A. Dusseau, S. Goldstein, A. Krishnamurthy, S. Lumetta, T. Eicken, and K. Yelick. Parallel Programming in Split-C. In Proc. Supercomputing, November 1993.
18. D. Culler and J. Singh. Parallel Computer Architecture: a Hard-ware/Software Approach. Morgan Kaufmann, 1999.
19. W. Dally and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In Proc. Design Automation Conf., pages 684-689, June 2001
20. R. Das, S. Eachempati, A. Mishra, V. Narayanan, and C. Das. Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs. In Proc. Int'l Symp. on High-Perf. Comp. Arch., February 2009.
21. S. Dwarkadas, A. Schaffer, R. Cottingham, A. Cox, P. Keleher, and W. Zwaenepoel. Parallelization of General Linkage Analysis Problems. Human Heredity, 44:127-141, 1994.
22. K. Gharachorloo, M. Sharma, S. Steely, and S. Van Doren. Architecture and design of AlphaServer GS320. In Proc. Int'l Conf. on Arch. Support for Prog. Lang. and Operating Systems, pages 13-24, November 2000.
23. G. Hendry, J. Chan, S. Kamil, L. Olifer, J. Shalf, L. Carloni, and K. Bergman. Silicon Nanophotonic Network-On-Chip Using TDM Arbitration. In Hot Interconnect, pages 88-95, August 2010.
24. Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar. A 5-GHz Mesh Interconnect for a Teraflops Processor. IEEE Micro, 27(5):51-61, 2007.
25. V. Issakov, H. Knapp, M. Tiebout, A. Thiede, W. Simburger, and L. Maurer. Comparison of 24 GHz low-noise mixers in CMOS and SiGe:C Technologies. In European Microwave Integrated Circuits Conference, pages 184-187, September 2009.
26. H. Ito, J. Inoue, S. Gomi, H. Sugita, K. Okada, and K. Masu. On-chip Transmission Line for Long Global Interconnects. In IEEE International Electron Devices Meeting. IEDM Technical Digest, pages 677-680, December 2004.
27. H. Ito, M. Kimura, K. Miyashita, T. Ishii, K. Okada, and K. Masu. A Bidirectional-and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications. IEEE Journal of Solid-State Circuits, 43(4):1020-1029, April 2008.
28. J. Kim, W. Dally, B. Towles, and A. Gupta. Microarchitecture of a High-Radix Router. In Proc. Int'l Symp. on Comp. Arch., pages 420-431, June 2005.
29. J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, V. Narayanan, M. S. Yousif, and C. R. Das. A Novel Dimensionally-decomposed Router for On-chip Communication in 3D Architectures. In Proc. Int'l Symp. on Comp. Arch., pages 138-149, June 2007.
30. N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi. Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. In Proc. Int'l Symp. on Microarch., pages 492-503, December 2006.
31. N. Kirman and J. Martinez. A Power-Efficient All-Optical On-Chip Interconnect Using Wavelength-Based Oblivious Routing. In Proc Int'l Conf. on Arch. Support for Prog. Lang. and Operating Systems, pages 15-28, March 2010.
32. K. Miyashita, T. Ishii, H. Ito, N. Ishihara, and K. Masu. An Over-12-Gbps On-Chip Transmission Line Interconnect with a Pre-Emphasis Technique in 90nm CMOS. In Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP, pages 303-306, October 2008.
33. N. Muralimanohar and R. Balasubramonian. Interconnect Design Considerations for Large NUCA Caches. In Proc. Int'l Symp. on Comp. Arch., pages 369-380, June 2007.
34. N. Jouppi N. Muralimanohar, R. Balasubramonian. Optimizing NUCA Organizations andWiring Alternatives for Large CachesWith CACTI 6.0. In Proc. Int'l Symp. on Microarch., pages 3-14, December 2007.
35. B. Nayfeh, K. Olukotun, and J. Singh. The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors. In Proc. Int'l Symp. on High-Perf. Comp. Arch., pages 74-84, February 1996.
36. J. Oh, M. Prvulovic, and A. Zajic. TLSync: Support for Multiple Fast Barriers Using On-Chip Transmission Lines. In Proc. Int'l Symp. on Comp. Arch., June 2011.
37. L. Peh andW. Dally. A Delay Model and Speculative Architecture for Pipelined Routers. In Proc. Int'l Symp. on High-Perf. Comp. Arch., pages 255-266, 2001.
38. D. Sanchez, G. Michelgeannakis, and C. Kozyrakis. An Analysis of On-Chip Interconnection Networks for Large-Scale Chip Multiprocessors. ACM Transactions on Architecture and Code Optimization, 7(1), 2010.
39. J. Seita, H. Ito, K. Okada, T. Sato, and K. Masu. A Multi-Drop Transmission-Line Interconnect in Si LSI. In Asia and South Pacific Design Automation Conference, pages 118-119, January 2007.
40. A. Shacham, K. Bergman, and L. Carloni. On the Design of a Photonic Network-on-Chip. In First Proc. Int'l Symp. on Networks-on-Chip, pages 53-64, May 2007.
41. A. Udipi, N. Muralimanohar, and R. Balasubramonian. Towards Scalable, Energy-Efficient, Bus-Based On-chip Networks. In Proc. Int'l Symp. on High-Perf. Comp. Arch., pages 1-12, January 2010.
42. D. Vantrease et al. Corona: System Implications of Emerging Nanophotonic Technology. In Proc. Int'l Symp. on Comp. Arch., June 2008.
43. D. Wentzlaff et al. On-Chip Interconnection Architecture of the Tile Processor. IEEE Micro, 27(5):15-31, 2007.
44. S.Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In Proc. Int'l Symp. on Comp. Arch., pages 24-36, June 1995.
45. J. Xue, A. Garg, B. Ciftcioglu, J. Hu, S. Wang, I. Savidis, M. Jain, R. Berman, P. Liu, M. Huang, H. Wu, E. Friedman, G. Wicks, and D. Moore. An Intra-Chip Free-Space Optical Interconnect. In Pro. Int'l Symp. on Comp. Arch., pages 94-105, June 2010.