Power reduction of CMP communication networks via rf-interconnects

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue 2008 PROCEEDINGS, 2008, Pages 376-387

  Chang, M C Frank ^a   Cong, Jason ^a   Kaplan, Adam ^a   Liu, Chunyue ^a   Naik, Mishali ^a   Premkumar, Jagannath ^a   Reinman, Glenn ^a   Socher, Eran ^a   Tam, Sai Wang ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA REDUCTION; BANDWIDTH ALLOCATIONS; BANDWIDTH DEMAND; CHIP MULTIPROCESSOR; COMMUNICATION NETWORKS; INTERCONNECT DESIGN; MULTICAST; ON CHIPS; ON-CHIP INTERCONNECTION NETWORK; POWER DISSIPATION; POWER REDUCTIONS; PROCESSING CORE; RADIO FREQUENCIES; RECONFIGURABLE NETWORK; TRANSMISSION LINE;

BANDWIDTH; EVAPORATIVE COOLING SYSTEMS; INTERCONNECTION NETWORKS; RADIO BROADCASTING; RADIO TRANSMISSION; TELECOMMUNICATION NETWORKS;

ELECTRIC NETWORK TOPOLOGY;

EID: 66749122976     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2008.4771806     Document Type: Conference Paper

References (23)

1. N. Agarwal, L-S Peh, and N. Jha. Garnet: A detailed interconnection network model inside a full-system simulation framework. Technical Report CE-P08-001, Dept. of Electrical Engineering, Princeton University, 2007.
2. B.M. Beckmann and D.A. Wood. TLC: Transmission line caches. In Proceedings of MICRO-36, December 2003.
3. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. Technical Report TR-811-08, Princeton University, 2008.
4. M. F. Chang, I. Verbauwhede, C. Chien, Z. Xu, J. Kim, J. Ko, Q. Gu, and B. Lai. Advanced RF/baseband interconnect schemes for inter- and intra-ulsi communications. In IEEE Transactions on Electron Devices, July 2005.
5. M.F. Chang, J. Cong, A. Kaplan, M. Naik, G. Reinman, E. Socher, and S-W. Tarn. CMP network-on-chip overlaid with multi-band RF-interconnect. In Proceedings of HPCA-14, February 2008.
6. M.F. Chang, V.P. Roychowdhury, L. Zhang, H. Shin, and Y. Qian. RF/wireless interconnect for inter- and intra-chip communications. Proceedings of the IEEE, 89(4), April 2001.
7. M.F. Chang, E. Socher, R. Tarn, J. Cong, and G. Reinman. RF interconnects for communications on-chip. In International Symposium on Physical Design (ISPD), April 2008.
8. L. Cheng, N. Muralimanohar, K. Ramani, R. Balasubramonian, and J.B. Carter. Interconnect-aware coherence protocols for chip multiprocessors. In Proceedings of ISCA-33, June 2006.
9. J. Cong and D.Z. Pan. Interconnect estimation and planning for deep submicron designs. In Proceedings of DAC-36, 1999.
10. W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, 2004.
11. W.J. Dally. Express cubes: Improving the performance of k-ary n-cube interconnection networks. IEEE Transactions on Computers, 40(9), 1991.
12. C. Grecu, A. Ivanov, P. Pande, A. Jantsch, E. Salminen, U. Ogras, and R. Marculescu. Towards open network-on-chip benchmarks. In International Symposium on Networks-on-Chip, May 2007.
13. R. Ho, K.W. Mai, and M. Horowitz. The future of wires. Proceedings of the IEEE, 89(4), April 2001.
14. Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald Graham, and Chung-Kuan Cheng. Communication latency aware low power noc synthesis. In DAC '06: Proceedings of the 43rd annual conference on Design automation, 2006.
15. N. E. Jerger, L-S Peh, and M. Lipasti. Virtual circuit tree multicasting: A case for on-chip hardware multicast support. In International Symposium on Computer Architecture (ISCA), 2008.
16. M. Mercaldi Kim, J. Davis, M. Oskin, and T. Austin. Polymorphic on-chip networks. In International Symposium on Computer Architecture(ISCA-35), June 2008.
17. N. Kirman, M. Kirman, R.K. Dokania, J.F. Martinez, A.B. A psel, M.A. Watkins, and D.H. Albonesi. Leveraging optical technology in future bus-based chip multiprocessors' In Proceedings of MICRO-39, December 2006.
18. R. Kumar, N. Jouppi, and D. Tullsen. Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling. In 32nd International Symposium on Computer Architecture, June 2005.
19. P. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner. Simics: A full system simulation platform. In IEEE Computer, Feb 2002.
20. U.Y Ogras and R. Marculescu. It's a small world after all: Noc performance optimization via long-range link insertion. IEEE Transactions on VLSI Systems, 14(7), July 2006.
21. J.D. Owens, W.J. Dally, R. Ho, D.N. Jayasimha, S.W. Keckler, and L-S. Peh. Research challenges for on-chip interconnection networks. IEEE Micro, 27(5):96-108, 2007.
22. A. Pinto, L. Carloni, and A. Sangiovanni-Vincentelli. Constraint-driven communication synthesis. In Design Automation Conference, June 2002.
23. H. Wang, X. Zhu, L-S. Peh, and S. Malik. Orion: A power-performance simulator for interconnection networks. In Proceedings of MICRO-35, November 2002.