Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

Solid-State Electronics

Volumn 74, Issue , 2012, Pages 114-120

  Najmzadeh, M ^a   Bouvet, D ^a   Grabinski, W ^a   Sallese, J M ^a   Ionescu, A M ^a  

^a EPFL   (Switzerland)

Author keywords

Gate all around Si nanowire MOSFETs; Highly doped accumulation mode regime; Local stressors as CMOS boosters; Scattering mechanism in nanoscale; Stress limited oxidation; TCAD Sentaurus Device simulation

Indexed keywords

ACCUMULATION MODES; BULK MOBILITY; CHANNEL DOPINGS; CONDUCTION MECHANISM; DENSE ARRAYS; DEVICE SIMULATIONS; ELECTRICAL CHARACTERISTIC; GATE-ALL-AROUND; HIGH TEMPERATURE PERFORMANCE; IONIZED IMPURITIES; LOCAL OXIDATION; METAL-GATE; MOBILITY REDUCTION; NANO SCALE; NMOSFETS; ROOM TEMPERATURE; SI NANOWIRE; UNIAXIAL TENSILE; UNIAXIAL TENSILE STRAIN;

ELECTRIC BREAKDOWN; ELECTRON MOBILITY; NANOWIRES; SILICON; TENSILE STRESS;

MOSFET DEVICES;

EID: 84861846735     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2012.04.021     Document Type: Conference Paper

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