Charge-based modeling of junctionless double-gate field-effect transistors

IEEE Transactions on Electron Devices

Volumn 58, Issue 8, 2011, Pages 2628-2637

  Sallese, Jean Michel ^a   Chevillon, Nicolas ^b   Lallement, Christophe ^b   Iñiguez, Benjamin ^c   Prégaldiny, Fabien ^b  

^a EPFL   (Switzerland)

^b UNIVERSITÉ DE STRASBOURG   (France)

^c UNIVERSITAT ROVIRA I VIRGILI   (Spain)

Author keywords

FETs; MOS devices; semiconductor device modeling; silicon devices; transistors

Indexed keywords

ANALYTICAL MODEL; CHARGE POTENTIALS; DEEP DEPLETION; DG MOSFETS; DOPING DENSITIES; DOUBLE-GATE; FETS; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; SEMICONDUCTOR DEVICE MODELING; SILICON CHANNEL; SILICON DEVICES; TECHNOLOGICAL PARAMETERS;

COMPUTER SIMULATION; MOS DEVICES; MOSFET DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DOPING; TRANSISTORS;

SEMICONDUCTOR DEVICE MODELS;

EID: 79960837040     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2156413     Document Type: Article

References (9)

1. C.W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, "Junction-less multigate field-effect transistor," Appl. Phys. Lett., vol. 94, no. 5, p. 053511, Feb. 2009.
2. J. P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions," Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010.
3. A. Pfitzner, M. Staniewski, and M. Strzyga, "DC characteristics of junction vertical slit field-effect transistor (JVeSFET)," in Proc. 16th Int. Conf. MIXDES, Lodz, Poland, Jun. 25-27, 2009, pp. 420-423.
4. M. Weis, A. Pfitzner, K. Kasprowicz, Y.-W. Lin, T. Fischer, R. Emling, M. Marek-Sadowska, D. Schmitt-Landsiedel, and W. Maly, "Low power SRAM cell using vertical slit field effect transistor (VeSFET)," in Proc. ESSCIRC Fringe P6, 2008.
5. E. Rauly, B. Iñiguez, and D. Flandre, "Investigation of deep submicron single and double gate SOI MOSFETs in accumulation mode for enhanced performance," Electrochem. Solid-State Lett., vol. 4, no. 3, pp. G28-G30, Mar. 2001.
6. B. Iñíguez, B. Gentinne, V. Dessard, and D. Flandre, "A physically-based continuous model for accumulation-mode SOI pMOSFETs," IEEE Trans. Electron Devices, vol. 46, no. 12, pp. 2295-2303, Dec. 1999. (Pubitemid 30540693)
7. J.-M. Sallese, F. Krummenacher, F. Prégaldiny, C. Lallement, A. Roy, and C. Enz, "A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism," Solid State Electron., vol. 49, no. 3, pp. 485-489, Mar. 2005. (Pubitemid 40119974)
8. J.-M. Sallese, N. Chevillon, F. Prégaldiny, C. Lallement, and B. Iñiguez, "The equivalent-thickness concept for doped symmetric DG MOSFETs," IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 2917-2924, Nov. 2010.
9. Y. Taur, "Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2861-2869, Dec. 2001. (Pubitemid 34091900)