Properties of accumulation-mode multi-gate field-effect transistors

Japanese Journal of Applied Physics

Volumn 48, Issue 3, 2009, Pages 034502-

  Colinge, Jean Pierre ^a   Lederer, Dimitri ^a,c   Afzalian, Aryan ^a   Yan, Ran ^a   Lee, Chi Woo ^a   Akhavan, Nima Dehdashti ^a   Xiong, Weize ^a,b  

^a UNIVERSITY COLLEGE CORK   (Ireland)

^b TEXAS INSTRUMENTS   (United States)

^c Ballincollig Co   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

ACCUMULATION MODES; CONDUCTION MECHANISM; DIGITAL APPLICATIONS; ELECTRICAL PERFORMANCE; ELECTROSTATIC CONTROL; EXPERIMENTAL DATA; FIN WIDTHS; FULLY DEPLETED; GATE FIELD; GATE LENGTH; HEAVILY DOPED; METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS; MOSFETS; P-TYPE; SHORT-CHANNEL DEVICES; SHORT-CHANNEL EFFECT; SIDE-CHANNEL; SILICON-ON-INSULATOR; SIMULATION DATA; SOI-MOSFETS; SURROUNDING-GATE; TRIPLE-GATE;

AMPLITUDE MODULATION; DIGITAL DEVICES; ELECTROSTATIC DEVICES; FINS (HEAT EXCHANGE); METALLIC COMPOUNDS; MOS DEVICES; MOSFET DEVICES; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY;

FIELD EFFECT TRANSISTORS;

EID: 67650831719     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.48.034502     Document Type: Article

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