Challenges in the design of high-speed clock and data recovery circuits

IEEE Communications Magazine

Volumn 40, Issue 8, 2002, Pages 94-101

  Razavi, Behzad ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION DETECTORS; FLIP FLOP CIRCUITS; LOW PASS FILTERS; MONOLITHIC INTEGRATED CIRCUITS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS; VLSI CIRCUITS;

CLOCK AND DATA RECOVERY; D FLIPFLOP; DATA RECOVERY CIRCUITS; HIGH SPEED CLOCK; PHASE DETECTOR;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036688038     PISSN: 01636804     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCOM.2002.1024421     Document Type: Article

References (8)

1. A self-correcting clock recovery circuit
2. A 52MHz and 155MHz clock recovery PLL
3. A versatile clock recovery architecture and monolithic implementation
4. Clock recovery from random binary data
5. A 10-Gb/s CMOS clock and data recovery circuit with a half rate linear phase detector
6. A Si bipolar phase and frequency detector for clock extraction up to 8 Gb/s
7. A 0.155, 0.622, and 2.488 Gb/s automatic bit rate selecting clock and data recovery IC for bit rate transparent SDH systems