Interconnect effort - a unification of repeater insertion and logical effort

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2003-January, Issue , 2003, Pages 55-61

  Srinivasaraghavan, Srividya ^a   Burleson, Wayne ^a  

^a University of Massachusetts   (United States)

Author keywords

Chromium; Computer Society; Delay lines; Repeaters; Very large scale integration; Wire

Indexed keywords

CHROMIUM; DESIGN; ELECTRIC DELAY LINES; PRODUCT DESIGN; TELECOMMUNICATION REPEATERS; VLSI CIRCUITS; WIRE;

DEEP SUB-MICRON DESIGNS; HSPICE SIMULATIONS; INTERCONNECT CIRCUITS; LOGIC CIRCUITRY; LOGICAL EFFORT; NON-UNIFORM; REPEATER INSERTION; STANDARD ASSUMPTIONS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 4444242466     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2003.1183353     Document Type: Conference Paper

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