Asynchronous wave pipelines for high throughput datapaths

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 1998, Pages 283-286

  Hauck, O ^a   Huss, S A ^a  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTATION THEORY; ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COMPUTER SOFTWARE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

ASYNCHRONOUS OPERATION; ASYNCHRONOUS WAVES; GATE-LEVEL PIPELINING; HANDSHAKE PROTOCOL; HSPICE SIMULATIONS; MAXIMIZE THROUGHPUT; PIPELINE ARCHITECTURE; SYNCHRONOUS DESIGNS;

THROUGHPUT; VLSI CIRCUITS;

MICROPIPELINES; WAVE PIPELINES;

EID: 0032260102     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1998.813322     Document Type: Conference Paper

References (15)

1. L. W. Cotten, "Maximum-rate pipeline systems", 1969 AFIPS Proc. Spring Joint Computer Conf., vol. 34, Montvale, NJ: AFIPS Press, pp. 581-586, May 1969.
2. Ivan E. Sutherland, "Micropipelines", Communications of the ACM, 32(6):720-738, June 1989.
3. Debabrata Ghosh and S. K. Nandy, "Design and Realization of High-Performance Wave-Pipelined 8×8 Multiplier in CMOS Technology", IEEE Trans, on VLSI, vol. 3, no. 1, pp. 36-48, March 1995.
4. X. Zhang and R. Sridhar, "CMOS Wave Pipelining Using Transmission Gate Logic", Proceedings of the IEEE International ASIC Conference and Exhibit, Rochester, NY, 1994.
5. W. Lien and W. Burleson, "Wave-Domino Logic: Theory and Applications", IEEE Trans, on Circuits and Systems, vol. 42, no. 2, February 1995.
6. Sanu Mathew and Ramalingam Sridhar, "Efficient Clocking of a Wave-Domino Pipeline", Proceedings IEEE Intern. Symp. on Circuits and Systems, pp. 1832-1835, 1997.
7. F. Klass and M. Flynn, "A 16 X 16-bit Static CMOS Wave-Pipelined Multiplier", Proceedings IEEE Intern. Symp. on Circuits and Systems, pp. 143-146, 1994.
8. D. Wong, G. De Micheli, and M. Flynn, "Designing High-Performance Digital Circuits Using Wave Pipelining: Algorithms and Practical Experiences", IEEE Trans, on CAD, vol. 12, no. 1, January 1993.
9. Kevin J. Nowka, "High-Performance CMOS System Design Using Wave Pipelining", PhD Thesis, Computer Systems Laboratory, Stanford University, August 1995.
10. S. Hauck, "Asynchronous Design Methodologies: An Overview", Proceedings of the IEEE, 83(1), 1995.
11. O. Hauck, H. Sauerwein, and S. A. Huss, "Asynchronous VLSI Architectures for Huffman Codecs", to appear in Proceedings IEEE Intern. Symp. on Circuits and Systems, 1998.
12. Paul Day and J. Viv. Woods, "Investigation into Micropipeline Latch Design Styles", IEEE Trans, on VLSI, vol. 3, no. 2, June 1995.
13. Kenneth Y. Yun, Peter A. Beerel, and Julio Arceo, "High-Performance Asynchronous Pipeline Circuits", Proceedings ASYNC'96, pp. 17-28, March 1996.
14. Erik Brunvand, "Low Latency Self-Timed Flow-Through FI-FOs", Proceedings 16th Conference on Advanced Research in VLSI, pp. 76-90, March 1995.
15. N. Weste, K. Eshraghian, "Principles of CMOS VLSI Design", second edition, Addison-Wesley, 1993, p. 526.