Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 280-284

  Shah, Harshit ^a   Shiu, Pun ^a   Bell, Brian ^a   Aldredge, Mamie ^a   Sopory, Namarata ^a   Davis, Jeff ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP SUBMICRON TECHNOLOGY; GLOBAL INTERCONNECTS; WIRE NETWORKS;

APPROXIMATION THEORY; CALCULATIONS; COMPUTER SIMULATION; MATHEMATICAL MODELS; OPTIMIZATION; PERTURBATION TECHNIQUES; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036907334     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774614     Document Type: Conference Paper

References (13)

1. J.A. Davis, et al., Proc. IEEE, vol. 89, No. 3, pp. 305-324, March 2001.
2. ITRS 2001 edition. (http://public.itrs.net)
3. W.J. Dally, Proc. IITC, June 1999, pp. 15-17.
4. P. Larsson-Edefors, IEEE Trans. on Circuits and Systems-I, vol. 47, no.4 pp.602-606, Apr 2000.
5. A. Kowalczyk, et al., ISSCC Tech Digest, 2001, pp. 236-237
6. S. Rusu, et al., IEEE JSSC, vol. 35, no. 11, pp. 1539-1544, Nov. 2000.
7. H.B. Bakoglu and J.D. Meindl, IEEE TED, vol. ED-32, no.5, pp. 903-909, May 1985.
8. T. Sakurai, IEEE TED, vol. 40, pp. 118-124, Jan. 1993.
9. Bakoglu,H. B., "Circuits, Interconnections, and Packaging for VLSI", Addison Wesley 1990.
10. B. Gueskens and K.Rose, "Modeling Microprocessor Performance," Kluwer, Boston, 1998.
11. J. Culetu, et.al., Proc. DAC, June 1998, pp. 392-395
12. G. Sai-Halasz, Proc. of IEEE, vol. 83, no. 1, pp. 20-36 Jan. 1995.
13. http://www.mosis.org/Technical/Testdata/ (MOS models)