Polysilicon spacer gate technique to reduce gate charge of a trench power MOSFET

IEEE Transactions on Electron Devices

Volumn 59, Issue 3, 2012, Pages 738-744

  Saxena, Raghvendra Sahai ^a   Kumar, M Jagadesh ^b  

^a SOLID STATE PHYSICS LABORATORY   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

Gate charge; Miller capacitance; power MOSFET; simulation; trench

Indexed keywords

GATE CHARGES; MILLER CAPACITANCE; POWER MOSFET; SIMULATION; TRENCH;

POLYSILICON;

MOSFET DEVICES;

EID: 84857646280     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2176946     Document Type: Article

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