Novel simplified process for fabricating a very high density P-channel trench gate power MOSFET

IEEE Electron Device Letters

Volumn 21, Issue 7, 2000, Pages 365-367

  Nam, Kee Soo ^a   Lee, Ju Wook ^b   Kim, Sang Gi ^a   Roh, Tae Moon ^a   Park, Hoon Soo ^c   Koo, Jin Gun ^a   Cho, Kyung Ik ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c Uiduk University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BREAKDOWN OF SOLIDS; ELECTRIC RESISTANCE; ETCHING; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; MASKS; NITRIDES; POWER INTEGRATED CIRCUITS;

CELL DENSITY; SIDEWALL SPACERS; TRENCH GATE;

MOSFET DEVICES;

EID: 0034217338     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.847382     Document Type: Article

References (7)

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2. 2," IEEE Trans. Electron Devices, vol. ED-34, pp. 2329-2334, 1987.
3. K. Shenai, "Optimized trench MOSFET technologies for power devices," IEEE Trans. Electron Devices, vol. 39, pp. 1435-1443, 1992.
4. 2 specific on-resistance at 2.7V," in Proc. ISPSD'96, 1996, pp. 53-55.
5. 2 density with distributed voltage clamping," in IEDM Tech. Dig., 1997, pp. 363-366.
6. A. Narazaki et al., "A novel 30V p-channel trench gate power MOSFET with ultra low on-state-resistance at low-gate-voltage," in Proc. ISPSD'97, 1997, pp. 285-288.
7. D. Kinzer, D. Asselanis, and R. Carta, "Ultra-low Rdson 12V p-channel trench MOSFET," in Proc. ISPSD'99, 1999, pp. 303-306.