Switching performance of low-voltage n-channel trench MOSFETs

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2002, Pages 177-180

  Hueting, Ray J E ^a   Hijzen, E A ^a   Ludikhuize, A W ^a   'T Zandt, M A A ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DOPING (ADDITIVES); ELECTRIC BREAKDOWN; ELECTRIC POTENTIAL; ELECTRIC RECTIFIERS; OPTIMIZATION; SWITCHING; TRENCHING;

SYNCHRONOUS RECTIFIERS;

MOSFET DEVICES;

EID: 0036048350     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. A study of MOSFET performance in processor targeted buck and synchronous rectifier buck converter
2. Optimisation of N-channel trench MOS for power applications
3. An ultra dense trench-gated power MOSFET technology using a self-aligned process
4. Vertical N-channel MOSFETs for extremely high density memories: The impact of interface orientation on device performance
5. Trench DMOS technology for high current (> 100A) switching
6. The behavior of very high current density power MOSFET's
7. Fully self-aligned trench-gated power MOSFET utilising a cell pitch of 1 μm including a trench width of 0.2 μm