Design optimizations for tiled partially reconfigurable systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 6, 2011, Pages 1048-1061

  Koester, Markus ^a   Luk, Wayne ^a   Hagemeyer, Jens ^b   Porrmann, Mario ^b   Rückert, Ulrich ^c  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b UNIVERSITY OF PADERBORN   (Germany)

^c BIELEFELD UNIVERSITY   (Germany)

Author keywords

Communication macro; design automation; field programmable gate arrays (FPGAs); overlap graph; reconfigurable architectures

Indexed keywords

COMMUNICATION INFRASTRUCTURE; DESIGN AUTOMATION; DESIGN METHOD; DESIGN OPTIMIZATION; DESIGN STEPS; DEVICE RESOURCES; DYNAMIC RE-CONFIGURATION; DYNAMIC SYSTEM COMPONENTS; OVERLAP GRAPH; PARTIAL RECONFIGURATION; PARTIALLY RECONFIGURABLE ARCHITECTURES; PLACEMENT ALGORITHM; RECONFIGURABLE ARCHITECTURE; RECONFIGURABLE SYSTEMS; RUNTIMES; STATIC AND DYNAMIC; STATIC SYSTEMS; SYSTEM COMPONENTS;

COMMUNICATION; COMPUTER AIDED DESIGN; DYNAMIC LOADS; DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE ARCHITECTURES;

STRUCTURAL DESIGN;

EID: 84857359673     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2044902     Document Type: Article

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