Dedicated module access in dynamically reconfigurable systems

20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Volumn 2006, Issue , 2006, Pages

  Hagemeyer, J ^a   Kettelhoit, B ^a   Porrmann, M ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION SYSTEMS; COMPUTER HARDWARE; SIGNAL PROCESSING;

DEDICATED SIGNALS; DYNAMIC RECONFIGURATION; HARDWARE CONFIGURATIONS; RUN TIME;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33847119985     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639446     Document Type: Conference Paper

References (7)

1. Xilinx. Virtex Series Configuration Architecture User Guide, Xilinx Application Note 151. Xilinx, March 2003.
2. Xilinx. Xilinx Virtex-II Platform FPGA User Guide. March 2005.
3. D. Lim and M. Peattie. Two flows for partial reconfiguration: module based or small bit manipulation, Xilinx Application Note 290. Xilinx, 2002.
4. P. Sedcole, B. Blodget, J. Anderson, P. Lysaght and T. Becker. Modular partial reconfiguration in Virtex FPGAs. In Proceedings of the 15th International Conference on Field Programmable Logic and Applications, Tampere, Finland, August 2005.
5. H. Kalte, M. Porrmann and U. Rückert. System-on-Programmable-Chip Approach Enabling Online Fine-Grained ID-Placement. In Proceedings of the 11th Reconfigurable Architectures Workshop, 2004.
6. J. Becker, T. Becker and M. Hübner. Real-Time LUT-based Network Topologies for Dynamic and Partial Self-Reconfiguration. In Proceedings of the 12th International Conference on Very Large Scale Integration VLSI-SoC, Darmstadt, December 2003.
7. H. Kalte, L. Gareth, M. Porrmann and U. Rückert. REPLICA: A bitstream manipulator filter for module relocation in partial reconfigurable systems. In Proceedings of the 19th International Parallel and Distributed Processing Symposium, Reconfigurable Architectures Workshop, 2005.