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Volumn , Issue , 2007, Pages 35-44

Enhancing relocatability of partial bitstreams for run-time reconfiguration

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SOFTWARE PROTOTYPING; SOFTWARE RADIO;

EID: 47349102172     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2007.51     Document Type: Conference Paper
Times cited : (74)

References (20)
  • 1
    • 35248823220 scopus 로고    scopus 로고
    • A self-reconfiguring platform
    • Field-Programmable Logic and Applications, Springer
    • B. Blodget, P. James-Roxby, E. Keller, S. McMillan, and P. Sundararajan. A self-reconfiguring platform. In Field-Programmable Logic and Applications, LNCS 2778, pages 565-574. Springer, 2003.
    • (2003) LNCS , vol.2778 , pp. 565-574
    • Blodget, B.1    James-Roxby, P.2    Keller, E.3    McMillan, S.4    Sundararajan, P.5
  • 3
    • 0003740827 scopus 로고    scopus 로고
    • PARBIT: A tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (FPGAs)
    • Technical Report WUCS-01-13, Washington University, Department of Computer Science
    • E. Horta and J. W. Lockwood. PARBIT: A tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (FPGAs). Technical Report WUCS-01-13, Washington University, Department of Computer Science, 2001.
    • (2001)
    • Horta, E.1    Lockwood, J.W.2
  • 4
    • 14244258231 scopus 로고    scopus 로고
    • M. Hübner, T. Becker, and J. Becker. Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. In 1Proceedings of the 17th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 28-32. ACM Press, 2004.
    • M. Hübner, T. Becker, and J. Becker. Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. In 1Proceedings of the 17th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 28-32. ACM Press, 2004.
  • 8
    • 34548059402 scopus 로고    scopus 로고
    • Enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration on Xilinx FPGAs
    • IEEE
    • P. Lysaght, B. Blodget, J. Mason, J. Young, and B. Bridgford. Enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration on Xilinx FPGAs. In Field Programmable Logic and Applications, pages 12-17. IEEE, 2006.
    • (2006) Field Programmable Logic and Applications , pp. 12-17
    • Lysaght, P.1    Blodget, B.2    Mason, J.3    Young, J.4    Bridgford, B.5
  • 9
    • 84893813102 scopus 로고    scopus 로고
    • Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip
    • IEEE Computer Society
    • J. Mignolet, V. Nollet, P. Coene, D. Verkest, and V. Lauwreins. Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip. In Design, Automation and Test in Europe (DATE), pages 986-991. IEEE Computer Society, 2003.
    • (2003) Design, Automation and Test in Europe (DATE) , pp. 986-991
    • Mignolet, J.1    Nollet, V.2    Coene, P.3    Verkest, D.4    Lauwreins, V.5
  • 10
    • 35248895399 scopus 로고    scopus 로고
    • A reconfigurable platform for real-time embedded video image processing
    • Field-Programmable Logic and Applications, Springer
    • N. P. Sedcole, P. Y. K. Cheung, G. A. Constantinides, and W. Luk. A reconfigurable platform for real-time embedded video image processing. In Field-Programmable Logic and Applications, LNCS 2778, pages 606 - 615. Springer, 2003.
    • (2003) LNCS , vol.2778 , pp. 606-615
    • Sedcole, N.P.1    Cheung, P.Y.K.2    Constantinides, G.A.3    Luk, W.4
  • 12
    • 33746868940 scopus 로고    scopus 로고
    • Compilation and management of phase-optimized reconfigurable systems
    • IEEE
    • H. Styles and W. Luk. Compilation and management of phase-optimized reconfigurable systems. In Field-Programmable Logic and Applications, pages 311-316. IEEE, 2005.
    • (2005) Field-Programmable Logic and Applications , pp. 311-316
    • Styles, H.1    Luk, W.2
  • 14
    • 0032097108 scopus 로고    scopus 로고
    • Improving functional density using run-time circuit reconfiguration
    • M.Wirthlin and B. Hutchings. Improving functional density using run-time circuit reconfiguration. IEEE Transactions on VLSI Systems, 6(2):247-256, 1998.
    • (1998) IEEE Transactions on VLSI Systems , vol.6 , Issue.2 , pp. 247-256
    • Wirthlin, M.1    Hutchings, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.