REPLICA2Pro: Task relocation by bitstream manipulation in virtex-II/Pro FPGAs

Proceedings of the 3rd Conference on Computing Frontiers 2006, CF '06

Volumn 2006, Issue , 2006, Pages 403-412

  Kalte, Heiko ^a   Porrmann, Mario ^b  

^a UNIVERSITY OF WESTERN AUSTRALIA   (Australia)

^b UNIVERSITY OF PADERBORN   (Germany)

Author keywords

Bitstream manipulation; FPGA; Reconfigurable computing; Task relocation

Indexed keywords

ALLOCATION PROCESSES; BITSTREAM MANIPULATION; RECONFIGURABLE COMPUTING;

COMPUTER HARDWARE; DIGITAL FILTERS; PROBLEM SOLVING; RESOURCE ALLOCATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34247384705     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1128022.1128045     Document Type: Conference Paper

References (12)

1. H. Kalte, M. Porrmann, and U. Rückert. System-on-programmable- chip approach enabling online fine-grained 1D-placement. In Proceedings of the 11th Reconfigurable Architectures Workshop (RAW 2004), Santa Fé, New Mexico, 2004.
2. M. Ullmann, M. Hübner, B. Grimm, and J. Becker. An fpga run-time system for dynamical on-demand reconfiguration. In Proc. of the 18th International Parallel and Distributed Processing Symposium, 2004.
3. A. Ahmadinia, C. Bobda, S. Fekete, T. Haller, A. Linarth, M. Majer, J. Teich, and J. van der Veen. The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. In Proceedings of the 2005 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, USA, April 17-20, 2005.
4. H. Kalte, G. Lee, M. Porrmann, U. Rückert: Study on Column Wise Design Compaction for Reconfigurable Systems. In: Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), Brisbane, Australia, December 6-8, 2004.
5. E. Horta, J. W. Lockwood, PARBIT: A tool to transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs). Tech. Rep. WUCS-01-13, Washington University, July 2001.
6. K. Compton, Z. Li, J. Coolley, S. Knol: Configuration Relocation and Defragmentation for Run-Time Reconfigurable Computing, IEEE Transactions on VLSI Systems, Vol. 10, No. 3, June 2002.
7. H. Kalte, G. Lee, M. Porrmann, U. Rückert: REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems. In Proc. of the 12th Reconfigurable Architectures Workshop (RAW), Denver, Colorado, USA, April 2005.
8. Xilinx Inc.: Xilinx Virtex-II Pro anilXilinx Virtex-II Pro X FPGA user guide, 2005. URL: http://www.xilinx.xom
9. Xilinx Application Notes 290: Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations, 2002, http://www.xilinx.com.
10. H. Kalte, M. Porrmann and U. Rückert: A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs. In Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, 2002.
11. M. Köster, H. Kalte, M. Porrmann: Task Placement for Heterogeneous Reconfigurable Architectures. In: Proceedings of the IEEE International Conference on FieldProgrammable Technology (FPT), Singapore, December 11-14, 2005. (Accepted for publication)
12. OpenCores: http://www.OpenCores.org