Run-time partial reconfiguration for removal, placement and routing on the Virtex-II Pro

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2007, Pages 679-683

  Raaijmakers, Stefan ^a   Wong, Stephan ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

FPGA; Reconfigurable Computing; Routing; Run Time Partial Reconfiguration

Indexed keywords

BIT STREAMS; DYNAMIC PARTIAL RECONFIGURATIONS; FPGA; HARDWARE MODULES; PARTIAL RECONFIGURATIONS; PLACEMENT AND ROUTING; RE-CONFIGURATIONS; RECONFIGURABLE; RECONFIGURABLE COMPUTING; RECONFIGURABLE HARDWARES; ROUTING; RUN-TIME PARTIAL RECONFIGURATION; XILINX TOOLS; XILINX VIRTEX;

GENERAL PURPOSE COMPUTERS; HARDWARE; INTERCONNECTION NETWORKS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 48149094365     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380744     Document Type: Conference Paper

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