Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs

20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Volumn 2006, Issue , 2006, Pages

  Hübner, Michael ^a   Schuck, Christian ^a   Becker, Jürgen ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

2 dimensional placement; Dynamic reconfiguration; Online routing; Virtex

Indexed keywords

COMPUTER HARDWARE; COMPUTER PROGRAMMING; LOGIC CIRCUITS; MICROCONTROLLERS; OPTIMIZATION; SOFTWARE ENGINEERING;

2 DIMENSIONAL PLACEMENT; DYNAMIC RECONFIGURATION; ONLINE ROUTING; VIRTEX;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33847121786     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639449     Document Type: Conference Paper

References (9)

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2. J. Becker, M. Hübner, M. Ullmann: "Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations", VLSI03, Darmstadt, Sep. 03
3. L. Benini, G. De Micheli: "Networks on Chip: A New Paradigm for Systems on Chip Design", Date 02, March 3-7, Paris France
4. J.C. Palma, A. Vieira de Melo, F. G. Moraes, N. Calazans, "Core Communication Interface for FPGAs", Proceedings of 15th Symposium on Integrated Circuits and Systems Design (SBCCI), 2002,Porto Alegre BRAZIL
5. http://www.xilinx.com/ise/design_tools/
6. http://www.xilinx.com/ise/embedded/edk.htm
7. M. Huebner, T. Becker, J. Becker "Real-Time LUT-Based Network Topologies for Dynamic and Partial FPGA Self-Reconfiguration", SBCCI04, Brasil
8. B. Blodget, S. McMillan: "A lightweight approach for embedded reconfiguration of FPGAs", DATE'03, Munich Germany
9. Xilinx, Virtex-II Platform FPGA User Guide UG002(v2.0), March, 23 2005