A self-adaptive on-line task placement algorithm for partially reconfigurable systems

IPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM

Volumn , Issue , 2008, Pages

  Lu, Yi ^a   Marconi, Thomas ^a   Gaydadjiev, Georgi ^a   Bertels, Koen ^a   Meeuws, Roel ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER NETWORKS; DISTRIBUTED PARAMETER NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INFORMATION MANAGEMENT;

PARALLEL AND DISTRIBUTED PROCESSING; RECONFIGURABLE SYSTEMS; RUN-TIME;

ADAPTIVE ALGORITHMS;

EID: 51049118364     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2008.4536505     Document Type: Conference Paper

References (15)

1. Intellectual Property. http://www.xilinx.com/ipcenter/.
2. Virtex 4 user guide. http://direct.xilinx.com/bvdocs/userguides/ ug070.pdf.
3. A. Ahmadinia, C. Bobda, S. P. Fekete, J. Teich, and J. C. van der Veen. Optimal free-space management and routing-conscious dynamic placement for reconfigurable devices. In IEEE Transactions on Computers, volume 56, pages 673-680, May 2007.
4. A. Ahmadinia, C. Bobda, and J. Teich. A dynamic scheduling and placement algorithm for reconfigurable hardware. In In Proceedings of 17th International Conference on Architecture of Computing Systems (ARCS 2004), volume 2981, pages 125-139. Springer-Verlag,, 2004.
5. K. Bazargan, R. Kastner, and M. Sarrafzadeh. Fast template placement for reconfigurable computing systems. In In IEEE Design and Test of Computers, volume 17, pages 68-83, 2000.
6. G. Brebner and O. Diessel. Chip-based reconfigurable task management. In the 11th International Conference on Field Programmable Logic and Application, FPL 2001, pages 182-191, Belfast, Northern Ireland, Aug 2001.
7. M. P. H. Kalte and U. Ruckert. System-on-programmable-chip approach enabling online fine-grained 1d-placement. In n 11th Reconfigurable Architectures Workshop (RAW 2004), 2004.
8. M. Koester, M. Porrmann, and H. Kalte. Task placement for heterogeneous reconfigurable architecture. In In Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT), Singapore, December 11-14, 2005.
9. Y. Lu and N. Bergmann. Dynamic loading of peripherals on reconfigurable system-on-chip. In In Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT), Singapore, December 11-14, 2005.
10. C. Steiger, H. Walder, and M. Platzner. Heuristics for online scheduling real-time tasks to partially reconfigurable devices. In the 13th International Conference on Field Programmable Logic and Application, FPL 2003, Lisbon, Portugal, Sept., 2003.
11. C. Steiger, H. Walder, M. Platzner, and L. Thiele. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), pages 224-235, Cancun, Mexico, December 2003.
12. J. Tabero, J. Septien, H. Mecha, and D. Mozos. Low fragmentation heuristic for task placement in 2d rtr hw management. In 14th International Conference on Field Programmable Logic and Application, FPL 2004, pages 241-250, Antwerp, Belgium, Sept. 2004.
13. S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov, and E. M. Panainte. The molen polymorphic processor. In IEEE Transactions on Computers archive, volume 53, Nov. 2004.
14. H. Walder and M. Platzner. Non-preemptive multitasking on fpgas: task placement and footprint transform. In In Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'02, June 2002.
15. H. Walder, C. Steiger, and M. Platzner. Fast online task placement on fpgas: Free space partitioning and 2d-hashing. In In Reconfigurable Architectures Workshop (RAW), Nice, France, April 2003.