Design optimizations to improve placeability of partial reconfiguration modules

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 976-981

  Koester, Markus ^a   Luk, Wayne ^a   Hagemeyer, Jens ^b   Porrmann, Mario ^b  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b UNIVERSITY OF PADERBORN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC LOADS; RECONFIGURABLE ARCHITECTURES;

AVERAGE NUMBERS; DESIGN OPTIMIZATION; DYNAMIC SYSTEM COMPONENTS; PARALLEL EXECUTIONS; PARTIAL RECONFIGURATION; PARTIALLY RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE SYSTEMS; SYSTEM COMPONENTS;

STRUCTURAL DESIGN;

EID: 70350068412     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090806     Document Type: Conference Paper

References (12)

1. K. Bazargan, R. Kastner, and M. Sarrafzadeh, "Fast template placement for reconfigurable computing systems," IEEE Design and Test of Computers, vol. Vol. 17, No. 1, pp. 68-83, 2000.
2. C. Steiger, H. Walder, and M. Platzner, "Operating systems for reconfigurable embedded platforms: Online scheduling of real-time tasks," IEEE Transactions on Computers, vol. 53, no. 11, pp. 1393-1407, 2004.
3. M. Handa and R. Vemuri, "Area fragmentation in reconfigurable operating systems," in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms. CSREA Press, 2004, pp. 77-83.
4. A. Ahmadinia, C. Bobda, M. Bednara, and J. Teich, "A new approach for on-line placement on reconfigurable devices," in 18th International Parallel and Distributed Processing Symposium (IPDPS 2004). IEEE Computer Society, 2004.
5. Y. Lu, T. Marconi, G. N. Gaydadjiev, K. Bertels, and R. J. Meeuws, "A self-adaptive on-line task placement algorithm for partially reconfigurable systems," in Proceedings of the 22nd Annual International Parallel and Distributed Processing Symposium (IPDPS 2008) - RAW2008, April 2008, pp. 1-8.
6. H. Kalte and M. Porrmann, "REPLICA2Pro: Task relocation by bitstream manipulation in Virtex-II/Pro FPGAs," in Proceedings of the ACM International Conference on Computing Frontiers, 2006.
7. T. Becker, W. Luk, and P. Cheung, "Enhancing relocatability of partial bitstreams for run-time reconfiguration," in IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society Press, 2007, pp. 35-44.
8. M. Koester, H. Kalte, and M. Porrmann, "Task placement for heterogeneous reconfigurable architectures," in Proceedings of the IEEE 2005 Conference on Field-Programmable Technology (FPT'05). IEEE Computer Society, 2005, pp. 43-50.
9. P. Lysaght, B. Blodget, J. Mason, B. Bridgford, and J. Young, "Enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAs," in 16th International Conference on Field Programmable Logic and Applications, 2006, pp. 12-17.
10. J. Hagemeyer, B. Kettelhoit, M. Koester, and M. Porrmann, "Design of homogeneous communication infrastructures for partially reconfigurable FPGAs," in Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA '07). CSREA Press, 2007.
11. M. Koester, H. Kalte, M. Porrmann, and U. Rückert, "Defragmentation algorithms for partially reconfigurable hardware," IFIP International Federation for Information Processing Series, vol. 240, pp. 41-53, 2007.
12. J. Angermeier, S. Fekete, T. Kamphans, D. Koch, N. Schweer, J. van der Veen, and J. Teich, "No-break dynamic defragmentation of recon-figurable devices," in Proceedings of International Conference on Field-Programmable Logic and Applications (FPL 08), Heidelberg, Germany, Sep. 2008.