A 667 MHz logic-compatible embedded DRAM featuring an asymmetric 2T gain cell for high speed on-die caches

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 2, 2012, Pages 547-559

  Chun, Ki Chul ^a   Jain, Pulkit ^a   Kim, Tae Ho ^a   Kim, Chris H ^a  

^a University of Minnesota   (United States)

Author keywords

2T gain cell; Cache; logic compatible eDRAM; random cycle; sense amplifier

Indexed keywords

CACHE; GAIN CELL; LOGIC-COMPATIBLE EDRAM; RANDOM CYCLE; SENSE AMPLIFIER;

CMOS INTEGRATED CIRCUITS;

CELLS;

EID: 84856481357     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2168729     Document Type: Article

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