A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110μsec

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 191-192

  Chun, Ki Chul ^a   Jain, Pulkit ^a   Kim, Tae Ho ^a   Kim, Chris H ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY ARCHITECTURE; CMOS PROCESSS; CURRENT SENSING SCHEMES; EMBEDDED DRAM; GAIN CELL; KEY FEATURE; RANDOM ACCESS; RANDOM CYCLE; RETENTION TIME;

CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE;

VLSI CIRCUITS;

EID: 77958002044     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560303     Document Type: Conference Paper

References (6)

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5. M. Ichihashi, VLSI Circuits Symp, pp. 366-369, 2005.
6. J. Sim, VLSI Circuits Symp, pp. 294-297, 2002.