0.5V Asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 366-369

  Ichihashi, Motoi ^a,b   Toda, Haruki ^a,c   Itoh, Yasuo ^a,c   Ishibashi, Koichiro ^a,b  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; LOGIC DESIGN; TRANSISTORS;

ASYMMETRIC THREE-TR. CELL (ATC); FEEDBACK SENSE AMPLIFIER; N-MOS TRANSISTORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 33645775026     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469406     Document Type: Conference Paper

References (6)

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2. A.J.Bhavnagarwala et al., "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," IEEE J. Solid-State Circuits, vol. 36, pp.658-665, April 2001.
3. M.Yamaoka et al., "0.4-V Logic Library Friendly SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array-Voltage Scheme," IEEE Symp. VLSI Circuits Dig., pp. 170-173, June 2002.
4. K. Hardee et al., "A 0.6V 205MHz 19.5ns tRC 16Mb Embedded DRAM," ISSCC Dig. Tech. Papers, pp. 200-201, Feb. 2004.
5. ASPLA : http://www.aspla.com/eng/
6. JEITA : http://www.jeita.or.jp/eiaj/english/news/pre39.htm