A 3T gain cell embedded DRAM utilizing preferential boosting for high density and low power on-die caches

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 6, 2011, Pages 1495-1505

  Chun, Ki Chul ^a   Jain, Pulkit ^a   Lee, Jung Hwa ^b   Kim, Chris H ^a  

^a University of Minnesota   (United States)

^b SAMSUNG Electronics   (South Korea)

Author keywords

3T gain cell; Cache; logic compatible eDRAM; low power; low voltage

Indexed keywords

CACHE; GAIN CELL; LOGIC-COMPATIBLE EDRAM; LOW-POWER; LOW-VOLTAGE;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DYNAMIC RANDOM ACCESS STORAGE; MONTE CARLO METHODS;

DIES;

EID: 79957668134     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2128150     Document Type: Article

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