A 500MHz random-access embedded 1Mb DRAM macro in bulk CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages

  Romanovsky, Sergey ^a   Katoch, Atul ^a   Achyuthan, Arun ^a   O'Connell, Cormac ^a   Natarajan, Sreedhar ^a   Huang, Chris ^b   Wu, Chuan Yu ^b   Wang, Min Jer ^b   Wang, C J ^b   Chen, Paul ^b   Hsieh, Rick ^b  

^a TSMC Design Technology Canada   (Canada)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BULK CMOS; DRAM MACRO; EMBEDDED DRAM; INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 49549087124     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523161     Document Type: Conference Paper

References (3)

1. J. Barth, H. Dreibelbis, E. Nelson et al., "Embedded DRAM Design and Architecture for the IBM 0.11μm ASIC Offering", IBM J. Res. Dev., vol. 46, no. 6, pp. 675-689, Nov. 2002.
2. J. Barth, W. Reohr, P. Parries et al., "A 500 MHz Random Cycle 1.5ns-Latency SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier", ISSCC Dig. Tech. Papers, pp. 486-467, Feb. 2006.
3. Y. Taito, T. Tanizaki, M. Kinoshita et al., "A High Density Memory for SoC with a 143MHz SRAM Interface Using Sense-Synchronized-Read/Write", ISSCC Dig. Tech. Papers, pp. 306-307 Feb. 2003.