A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 1, 2008, Pages 86-95

  Barth, John ^a   Reohr, William R ^b   Parries, Paul ^a   Fredeman, Gregory ^a   Golz, John ^a   Schuster, Stanley E ^b   Matick, Richard E ^b   Hunter, Hillery ^b   Tanner, Charles C ^a   Harig, Joseph ^a   Kim, Hoki ^a   Khan, Babar A ^a   Griesemer, John ^a   Havreluk, Robert P ^a   Yanagisawa, Kenji ^a   Kirihata, Toshiaki ^a   Iyer, Subramanian S ^a  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

DRAM chips; FET amplifiers; memory architecture; microprocessor chips; Silicon on Insulator

Indexed keywords

EID: 85008048111     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.2007.908006     Document Type: Article

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