A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 4, 2009, Pages 1216-1226

  Klim, Peter J ^a   Barth, John ^a   Reohr, William R ^b   Dick, David ^a   Fredeman, Gregory ^a   Koch, Gary ^a   Le, Hien M ^a   Khargonekar, Aditya ^a   Wilcox, Pamela ^a   Golz, John ^a   Kuang, Jente B ^c   Mathews, Abraham ^a   Law, Jethro C ^a   Luong, Trong ^a   Ngo, Hung C ^c   Freese, Ryan ^d   Hunter, Hillery C ^b   Nelson, Erik ^a   Parries, Paul ^a   Kirihata, Toshiaki ^a   Iyer, Subramanian S ^a   more..

^a IBM   (United States)

^b IBM RESEARCH   (United States)

^c IBM AUSTIN RESEARCH LABORATORY   (United States)

^d ADVANCED MICRO DEVICES   (United States)

Author keywords

45 nm; Cache; Embedded DRAM; SOI

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; PIPELINES; REPAIR;

45 NM; CACHE; CLOCK GENERATIONS; EMBEDDED DRAM; LINE VOLTAGES; ON CHIPS; PROGRAMMING VOLTAGES; READ-ONLY MEMORIES; REPAIR CONTROLS; SINGLE VOLTAGE SUPPLIES; SOI; SOI CMOS;

BUILT-IN SELF TEST;

EID: 63449138181     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2014207     Document Type: Conference Paper

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