1.5-V-operation ultralow power circuit of poly-si TFTs fabricated using the NAOS method

IEEE Transactions on Electron Devices

Volumn 59, Issue 2, 2012, Pages 385-392

  Kubota, Yasushi ^a,b   Matsumoto, Taketoshi ^b,c   Tsuji, Hiroshi ^b,c   Suzuki, Nobuhiko ^d   Imai, Shigeki ^a,b   Kobayashi, Hikaru ^b,c  

^a SHARP CORPORATION   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

^c OSAKA UNIVERSITY   (Japan)

^d HOYA CORPORATION   (Japan)

Author keywords

Driving circuit; liquid crystal display (LCD); low power consumption; nitric acid oxidation of silicon (NAOS); thin film transistor (TFT)

Indexed keywords

DRIVING CIRCUITS; GATE INSULATOR; GLASS SUBSTRATES; LOW POWER CONSUMPTION; NITRIC ACID OXIDATION; NITRIC ACID OXIDATION OF SILICON (NAOS); POLY-SI TFTS; POWER SUPPLY VOLTAGE; STACK STRUCTURE; SUPPLY VOLTAGES; ULTRA-LOW POWER; ULTRA-LOW POWER CONSUMPTION; ULTRA-THIN;

CHEMICAL VAPOR DEPOSITION; CRYSTAL STRUCTURE; ENERGY GAP; LIQUID CRYSTAL DISPLAYS; LIQUIDS; LOW POWER ELECTRONICS; NITRIC ACID; PLASMA DEPOSITION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SEMICONDUCTING ORGANIC COMPOUNDS; SILICON COMPOUNDS; SILICON OXIDES; SUBSTRATES; VANADIUM;

THIN FILM TRANSISTORS;

EID: 84856264626     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2175395     Document Type: Article

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