3D NoC using through silicon via: An asynchronous implementation

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011

Volumn , Issue , 2011, Pages 232-237

  Vivet, Pascal ^a   Dutoit, Denis ^a   Thonnart, Yvain ^a   Clermidy, Fabien ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING; 3D TECHNOLOGY; ASSEMBLY PROCESS; ASYNCHRONOUS LOGIC; AVAILABLE BANDWIDTH; EFFICIENT IMPLEMENTATION; NETWORK ON CHIP; SYSTEM-ON-CHIP; THROUGH SILICON VIAS; THROUGH-SILICON-VIA;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ASYNCHRONOUS SEQUENTIAL LOGIC; BANDWIDTH; THREE DIMENSIONAL; VLSI CIRCUITS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 83755172109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISoC.2011.6081643     Document Type: Conference Paper

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