Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2009, Pages 772-777

  Pares G ^a   Minoret, S ^a   Lugand, J F ^a   Huet, S ^a   Lapras, V ^a   Anciant, R ^a   Henry, D ^a   Sillon, N ^a   Dunne, B ^b  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING; BACK STEP; CMP PROCESS; CONFORMAL DEPOSITION; DEEP RIE; DEPOSITION PROCESS; ELECTRICAL CHARACTERIZATION; ETCHING PROCESS; FILLING MATERIALS; HIGH VOLTAGE; HIGH-VOLTAGE OPERATION; INTEGRATION APPROACH; KELVIN STRUCTURES; PLANARIZATION; PROCESS DEVELOPMENT; PROCESS FLOWS; PRODUCT APPLICATIONS; REDISTRIBUTION LAYERS; RING WIDTH; SILICON SURFACES; SPECIAL STRUCTURE; SPECIFIC TEST VEHICLE; STRESS FREE; TEST CHIPS; THROUGH SILICON VIAS; THROUGH-SILICON-VIA; TUNGSTEN METALLIZATION; VIA-FIRST;

ANTIREFLECTION COATINGS; BUILDING MATERIALS; CHEMICAL MECHANICAL POLISHING; ELECTRONICS PACKAGING; NANOTECHNOLOGY; SILICON WAFERS; TECHNOLOGY; TUNGSTEN;

CHEMICAL POLISHING;

EID: 77950929550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2009.5416444     Document Type: Conference Paper

References (9)

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