A fully-asynchronous low-power framework for GALS NoC integration

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 33-38

  Thonnart, Yvain ^a   Vivet, Pascal ^a   Clermidy, Fabien ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; LOW POWER ELECTRONICS; NETWORK ARCHITECTURE; NETWORK-ON-CHIP;

ASYNCHRONOUS LOGIC; ASYNCHRONOUS NETWORKS; BOTTOM UP APPROACH; COMMUNICATION INFRASTRUCTURE; DESIGN FLOWS; HARD MACRO; POWER REDUCTIONS; PROPOSED ARCHITECTURES;

INTEGRATED CIRCUIT DESIGN;

EID: 77953113725     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5457239     Document Type: Conference Paper

References (18)

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