3D Integration : A technological toolbox

2008 3rd International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2008

Volumn , Issue , 2008, Pages 375-378

  Poupon, Gilles ^a   Scannell, Mark ^a   Cioccio, Lea Di ^a   Henry, David ^a   Leduc, Patrick ^a   Clavelier, Laurent ^a   Sillon, Nicolas ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATIONS; BONDING TECHNOLOGIES; CHIP STACKING; DEVICE PERFORMANCE; HETEROGENEOUS SYSTEMS; HIGH DENSITIES; INNOVATIVE SYSTEMS; KEY TECHNOLOGIES; MICRO-ELECTRONIC DEVICES; ONE CHIPS; PROCESSING STAGES; SELF- ASSEMBLIES; SEMICONDUCTOR LAYERS; WAFER-THINNING PROCESS;

BONDING; CHIP SCALE PACKAGES; COPPER OXIDES; DIES; INTEGRATION; MICROSYSTEMS; TECHNOLOGY;

WAFER BONDING;

EID: 64049094669     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMPACT.2008.4783890     Document Type: Conference Paper

References (6)

1. Gilles Poupon et al., Special Issue of the IEEE Proceedings on 3D Integration Technology, 2008
2. Lea Di Cioccio et al., IMAPS Device Packaging Workshop, 2008, Scottsdale, USA
3. th electronic Components & Technology Conference (ECTC) 2008, Orlando
4. Patrick Leduc et al., Conf; VLSI 2007
5. Alan Mathewson et al., Proced. IEEE Electronic Systems Integration Conference (ESTC) 2007, Dresden
6. Francois Grossi et al., IMAPS Device Packaging Workshop, 2006, Scottsdale, USA