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Volumn , Issue , 2008, Pages 1003-1008

Serialized asynchronous links for NoC

Author keywords

Asynchronous; Network on chip; Point to point links; Serial

Indexed keywords

ASYNCHRONOUS; ASYNCHRONOUS LINKS; CLOCK SPEEDS; DESIGN REQUIREMENTS; FOUNDRY MODELS; NETWORK-ON-CHIP; POINT TO POINT; POINT-TO-POINT LINKS; REDUCED POWER CONSUMPTION; SERIAL; SERIAL LINKS; TRANSISTOR-LEVEL SIMULATIONS;

EID: 49749146712     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484812     Document Type: Conference Paper
Times cited : (12)

References (15)
  • 2
    • 4043150092 scopus 로고    scopus 로고
    • Xpipes: A network-on-chip architecture for gigascale systems-on-chip
    • D. Bertozzi and L. Benini, "Xpipes: A network-on-chip architecture for gigascale systems-on-chip," IEEE Circuits and Systems Magazine, vol. 4, pp. 18-31, 2004.
    • (2004) IEEE Circuits and Systems Magazine , vol.4 , pp. 18-31
    • Bertozzi, D.1    Benini, L.2
  • 3
    • 27344456043 scopus 로고    scopus 로고
    • AEthereal network on chip: Concepts, architectures, and implementations
    • K. Goossens, J. Dielissen, and A. Radulescu, "AEthereal network on chip: concepts, architectures, and implementations," IEEE Design & Test of Computers, vol. 22, pp. 414-21, 2005.
    • (2005) IEEE Design & Test of Computers , vol.22 , pp. 414-421
    • Goossens, K.1    Dielissen, J.2    Radulescu, A.3
  • 5
    • 84947211640 scopus 로고    scopus 로고
    • SoCBUS: Switched network on chip for hard real time embedded systems
    • D. Wiklund and L. Dake, "SoCBUS: switched network on chip for hard real time embedded systems," in IPDPS 2003.
    • IPDPS 2003
    • Wiklund, D.1    Dake, L.2
  • 6
    • 85013498045 scopus 로고    scopus 로고
    • Asynchronous on-chip networks
    • B. M. Al-Hashimi, Ed, IEE
    • M. Amde et al, "Asynchronous on-chip networks," in System-on-Chip: Next Generation Electronics, B. M. Al-Hashimi, Ed.: IEE, 2006, pp. 625-52.
    • (2006) System-on-Chip: Next Generation Electronics , pp. 625-652
    • Amde, M.1
  • 9
    • 21244484285 scopus 로고    scopus 로고
    • A. Morgenshtein et al, Comparative analysis of serial vs parallel links in NoC, in International Symposium on System-on-Chip Tampere, Finland, 2004, pp. 185-8.
    • A. Morgenshtein et al, "Comparative analysis of serial vs parallel links in NoC," in International Symposium on System-on-Chip Tampere, Finland, 2004, pp. 185-8.
  • 11
    • 33645011974 scopus 로고    scopus 로고
    • Low-power network-on-chip for high-performance SoC design
    • L. Kangmin, L. Se-Joong, and Y. Hoi-Jun, "Low-power network-on-chip for high-performance SoC design," IEEE Transactions VLSI Systems, vol. 14, pp. 148-60, 2006.
    • (2006) IEEE Transactions VLSI Systems , vol.14 , pp. 148-160
    • Kangmin, L.1    Se-Joong, L.2    Hoi-Jun, Y.3
  • 13
    • 0017525050 scopus 로고
    • Modular design of asynchronous circuits defined by graphs
    • R. David, "Modular design of asynchronous circuits defined by graphs," IEEE Transactions on Computers, vol. C-26, pp. 727-737, 1977.
    • (1977) IEEE Transactions on Computers , vol.C-26 , pp. 727-737
    • David, R.1
  • 15


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.