Polymer filling of medium density through silicon via for 3D-packaging

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2009, Pages 790-794

  Chausse, P ^a   Bouchoucha, M ^b   Henry, D ^a   Sillon, N ^a   Chapelon, L L ^b  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DRY FILM RESIST; INTEGRATION SCHEME; LIQUID POLYMERS; MECHANICAL AND ELECTRICAL PROPERTIES; POLYMER FILLING; POLYMER MATERIALS; PROCESS DEVELOPMENT; SET TOP BOX; SPIN-ON; TEST STRUCTURE; TEST WAFERS; THROUGH-SILICON-VIA; VIA FILLING;

ELECTRIC PROPERTIES; ELECTRONICS PACKAGING; FILLING; MECHANICAL PROPERTIES; SILICON WAFERS; THREE DIMENSIONAL;

POLYMERS;

EID: 77950953249     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2009.5416443     Document Type: Conference Paper

References (6)

1. L. Bonnot & Al, "3D integration program overview", April 2009.
2. A. Jouve & Al, "Facilitating Ultrathin Wafer Handling for TSV Processing", EPTC 2008, 9-12 december 2008, Singapour.
3. J. Charbonnier & Al, "Integration of a temporary carrier in a TSV Process Flow", EC TC 2009, 26-29 May 2009
4. D.Henry & Al, "Through silicon vias technology for cmos image sensors packaging: presentation of technology and electrical results", EPTC 2008, 9-12 december 2008, Singapour.
5. S. Cheramy & Al, "3D integration process flow for set-top box application: description of technology and electrical results", EMPC 2009, 17-18 June 2009, Rimini.
6. D. Henry & Al, "3D integration technology for set-top box application", 3DIC Conference - Sept. 28-30, 2009 - San Francisco - CA