Wafer level packaging technology development for CMOS image sensors using through silicon vias

Proceedings - 2008 2nd Electronics Systemintegration Technology Conference, ESTC

Volumn , Issue , 2008, Pages 141-148

  Charbonnier, J ^a   Henry, D ^a   Jacquet, F ^a   Aventurier, B ^a   Brunet Manquat, C ^a   Enyedi, G ^a   Bouzaida, N ^a   Lapras, V ^a   Sillon, N ^a  

^a CEA LETI   (France)

Author keywords

Advanced packaging; CMOS image sensors (CIS); Through silicon vias (TSV); Wafer level technologies

Indexed keywords

CHIP SCALE PACKAGES; DIGITAL CAMERAS; DIGITAL IMAGE STORAGE; ELECTRONICS PACKAGING; GLASS BONDING; IMAGE SENSORS; INTERCONNECTION NETWORKS; NONMETALS; PACKAGING; PAPER; PIXELS; SEMICONDUCTING SILICON COMPOUNDS; SENSORS; SILICON WAFERS; TECHNOLOGICAL FORECASTING; TECHNOLOGY; WAFER BONDING;

ADVANCED PACKAGING; CMOS IMAGE SENSORS (CIS); DEEP ETCHINGS; DESIGN RULES; ELECTRICAL CHARACTERIZATIONS; GLASS WAFERS; LOW TEMPERATURES; METALLIZATION; PACKAGING TECHNOLOGIES; SIDE WALLS; SILICON SUBSTRATES; THROUGH SILICON VIAS (TSV); WAFER LEVEL TECHNOLOGIES;

ELECTRONIC EQUIPMENT MANUFACTURE;

EID: 58149096521     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2008.4684340     Document Type: Conference Paper

References (7)

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2. N. Sillon et Al - "Innovative flip chip solution for System on Wafer concept" - 38 workshop September 2005 - Atlanta.
3. D. Henry et Al - "Through vias technology for System on wafer approach" - ENCAST Workshop Zurich - 08 & 09 november 2005.
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