Exploring DRAM Last Level Cache for 3D Network-on-Chip architecture

Advanced Materials Research

Volumn 403-408, Issue , 2012, Pages 4009-4018

  Xu, Thomas Canhao ^a,b   Liljeberg, Pasi ^a,b   Tenhunen, Hannu ^a,b  

^a UNIVERSITY OF TURKU   (Finland)

^b TURKU CENTRE FOR COMPUTER SCIENCE   (Finland)

Author keywords

3D IC; Chip multiprocessor; DRAM; Network on Chip; NUCA; SRAM

Indexed keywords

ACCESS LATENCY; CACHE SIZE; CHIP MULTIPROCESSOR; CYCLE ACCURATE; DYNAMIC RANDOM ACCESS MEMORY; FULL SYSTEM SIMULATORS; NETWORK ON CHIP; NETWORK-ON-CHIP ARCHITECTURES; NETWORK-ON-CHIP DESIGN; NOC DESIGN; NUCA; SRAM DESIGN; STATIC RANDOM ACCESS MEMORY;

LOGIC DESIGN; MEMORY ARCHITECTURE; ROUTERS; SERVERS; STATIC RANDOM ACCESS STORAGE; THREE DIMENSIONAL; VLSI CIRCUITS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 83255170570     PISSN: 10226680     EISSN: None     Source Type: Book Series    
DOI: 10.4028/www.scientific.net/AMR.403-408.4009     Document Type: Conference Paper

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